diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 86857c0..bf279b7 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -86,6 +86,16 @@
 	  Enabling this config adds support for the DDR memory controller
 	  on AM642 family of SoCs.
 
+config K3_AM62A_DDRSS
+	bool "Enable AM62A DDRSS support"
+	help
+	  The AM62A DDR subsystem comprises of a DDR controller, DDR PHY and
+	  wrapper logic to integrate these blocks into once device. The DDR
+	  subsystem is used to provide an interface to external SDRAM devices
+	  which can be utilized for storing programs or any other data.
+	  Enabling this option adds support for the DDR memory controller for
+	  the AM62A family of SoCs.
+
 endchoice
 
 config IMXRT_SDRAM
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
deleted file mode 100644
index 6c57dd9..0000000
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_OBJ_IF_H
-#define LPDDR4_16BIT_OBJ_IF_H
-
-#include "lpddr4_16bit_if.h"
-
-#endif  /* LPDDR4_16BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
deleted file mode 100644
index 5297348..0000000
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_STRUCTS_IF_H
-#define LPDDR4_16BIT_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_16bit_if.h"
-
-#endif  /* LPDDR4_16BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
deleted file mode 100644
index 7fee54f..0000000
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_32BIT_OBJ_IF_H
-#define LPDDR4_32BIT_OBJ_IF_H
-
-#include "lpddr4_32bit_if.h"
-
-#endif  /* LPDDR4_32BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
deleted file mode 100644
index 69b2a47..0000000
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_32BIT_STRUCTS_IF_H
-#define LPDDR4_32BIT_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_32bit_if.h"
-
-#endif  /* LPDDR4_32BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
index 8be0011..ba5d9a2 100644
--- a/drivers/ram/k3-ddrss/Makefile
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/
 #
 
 obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
@@ -8,10 +8,14 @@
 obj-$(CONFIG_K3_DDRSS) += lpddr4.o
 ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
 
-obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
-obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
-ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
+obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am6x.o
+obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am62a_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM62A_DDRSS) += -Idrivers/ram/k3-ddrss/am62a/
 
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
-ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am6x.o
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am64_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/am64/
+
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/j721e/
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
similarity index 78%
copy from drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
copy to drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
index 58ba340..1cd40c8 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
@@ -391,11 +391,11 @@
 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
 
-#define LPDDR4__DENALI_PHY_1053_READ_MASK                            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053_WRITE_MASK                           0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK             0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT                     0U
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH                    24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH                    30U
 #define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
 #define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
 
@@ -555,8 +555,8 @@
 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
 
-#define LPDDR4__DENALI_PHY_1060_READ_MASK                            0x07FF3F01U
-#define LPDDR4__DENALI_PHY_1060_WRITE_MASK                           0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_READ_MASK                            0x00003F01U
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK                           0x00003F01U
 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK         0x00000001U
 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT                 0U
 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH                 1U
@@ -571,254 +571,208 @@
 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
 
-#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK   0x07FF0000U
-#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT          16U
-#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH          11U
-#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
-#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
+#define LPDDR4__DENALI_PHY_1061_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_WIDTH                  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0
 
-#define LPDDR4__DENALI_PHY_1061_READ_MASK                            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_1061_WRITE_MASK                           0x01FF01FFU
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK        0x000001FFU
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT                0U
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH                9U
-#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
-#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_MASK       0x00000700U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH               3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0
 
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK   0x01FF0000U
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT          16U
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH           9U
-#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
-#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_MASK           0x07FF0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_WIDTH                  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0
 
-#define LPDDR4__DENALI_PHY_1062_READ_MASK                            0x01010000U
-#define LPDDR4__DENALI_PHY_1062_WRITE_MASK                           0x01010000U
-#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT       0U
-#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH       9U
-#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062
-#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0
+#define LPDDR4__DENALI_PHY_1062_READ_MASK                            0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK                           0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH          3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
 
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT       16U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH        1U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR        0U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET        0U
-#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062
-#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK     0x00001F00U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT  24U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH   1U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR   0U
-#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET   0U
-#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062
-#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK  0x07FF0000U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U
-#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
-#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
+#define LPDDR4__DENALI_PHY_1063_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1063_WRITE_MASK                           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1064_READ_MASK                            0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1064_WRITE_MASK                           0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK          0x000000FFU
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT                  0U
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH                  8U
-#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
-#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK       0x00000700U
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT               8U
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH               3U
-#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064
-#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK           0x07FF0000U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT                  16U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH                  11U
-#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
-#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
+#define LPDDR4__DENALI_PHY_1064_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1065_READ_MASK                            0x1F07FF1FU
-#define LPDDR4__DENALI_PHY_1065_WRITE_MASK                           0x1F07FF1FU
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK     0x0000001FU
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT             0U
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
-#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK  0x0007FF00U
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT          8U
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
-#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1065_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK     0x1F000000U
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT            24U
-#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
-#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_1066_READ_MASK                            0x001F07FFU
 #define LPDDR4__DENALI_PHY_1066_WRITE_MASK                           0x001F07FFU
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
-#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT            16U
-#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
-#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1067_READ_MASK                            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1067_WRITE_MASK                           0x001F07FFU
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
-#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1067_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1067_WRITE_MASK                           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT            16U
-#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
-#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0
 
-#define LPDDR4__DENALI_PHY_1068_READ_MASK                            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1068_WRITE_MASK                           0x001F07FFU
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068
-#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1068_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1068_WRITE_MASK                           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0
 
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT            16U
-#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
-#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0
 
-#define LPDDR4__DENALI_PHY_1069_READ_MASK                            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1069_WRITE_MASK                           0x001F07FFU
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069
-#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0
 
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT            16U
-#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH             5U
-#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
-#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
+#define LPDDR4__DENALI_PHY_1069_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1069_WRITE_MASK                           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
 
-#define LPDDR4__DENALI_PHY_1070_READ_MASK                            0x000F07FFU
-#define LPDDR4__DENALI_PHY_1070_WRITE_MASK                           0x000F07FFU
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
-#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070
-#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0
 
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK       0x000F0000U
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT              16U
-#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH               4U
-#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
-#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
 
-#define LPDDR4__DENALI_PHY_1071_READ_MASK                            0xFF3F07FFU
-#define LPDDR4__DENALI_PHY_1071_WRITE_MASK                           0xFF3F07FFU
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK   0x000007FFU
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT           0U
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH          11U
-#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071
-#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0
+#define LPDDR4__DENALI_PHY_1070_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1070_WRITE_MASK                           0x0000000FU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1070
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0
 
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK    0x003F0000U
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT           16U
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH            6U
-#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071
-#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0
+#define LPDDR4__DENALI_PHY_1071_READ_MASK                            0x03FF010FU
+#define LPDDR4__DENALI_PHY_1071_WRITE_MASK                           0x03FF010FU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0
 
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK    0xFF000000U
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT           24U
-#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH            8U
-#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
-#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
 
-#define LPDDR4__DENALI_PHY_1072_READ_MASK                            0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1072_WRITE_MASK                           0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT    0U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH    8U
-#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072
-#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK     0x0003FF00U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT             8U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH            10U
-#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072
-#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0
+#define LPDDR4__DENALI_PHY_1072_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1072_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0
 
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK  0x01000000U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT         24U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH          1U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR          0U
-#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET          0U
-#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
-#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
-
-#define LPDDR4__DENALI_PHY_1073_READ_MASK                            0x0000000FU
-#define LPDDR4__DENALI_PHY_1073_WRITE_MASK                           0x0000000FU
-#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK       0x0000000FU
-#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT               0U
-#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH               4U
-#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
-#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
-
-#define LPDDR4__DENALI_PHY_1074_READ_MASK                            0x03FF010FU
-#define LPDDR4__DENALI_PHY_1074_WRITE_MASK                           0x03FF010FU
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK    0x0000000FU
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT            0U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH            4U
-#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074
-#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0
-
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT         8U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH         1U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR         0U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET         0U
-#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074
-#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
-
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK    0x03FF0000U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT           16U
-#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH           10U
-#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
-#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
-
-#define LPDDR4__DENALI_PHY_1075_READ_MASK                            0x0000FF01U
-#define LPDDR4__DENALI_PHY_1075_WRITE_MASK                           0x0000FF01U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK      0x00000001U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT              0U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH              1U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR              0U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET              0U
-#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075
-#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0
-
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK    0x0000FF00U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT            8U
-#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH            8U
-#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075
-#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0
 
 #endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
new file mode 100644
index 0000000..69521c7
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1280_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH   11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_1280
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET          0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_1280
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH              3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_1280
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_1281_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH             32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_1281
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1282_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH        16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK  0x00FF0000U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH          8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH   4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1283_READ_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK                           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH         11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH         7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH        8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_1284_READ_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK                           0x01000707U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT       8U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH       3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET             0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_1284
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOSET                  0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1285_READ_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK                           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_WIDTH                 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_MASK   0x00007F00U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_WIDTH           7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH            5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOSET              0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1286_READ_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK                           0x01070301U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET    0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_MASK                 0x00000300U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_WIDTH                         2U
+#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK     0x00070000U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH             3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOSET                      0U
+#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_1287_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287_WRITE_MASK                           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_MASK             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_WIDTH                    27U
+#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_1287
+#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_1288_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_WIDTH                     6U
+#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_1288
+#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_1289_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_1289
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_1290_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH       32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_1290
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_1291_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_MASK          0x000007FFU
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_WIDTH                 11U
+#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1
+
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH            11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1
+
+#define LPDDR4__DENALI_PHY_1292_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_WIDTH                   11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_1292
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1
+
+#define LPDDR4__DENALI_PHY_1293_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_1293
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_1294_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_1294
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_MASK      0x03000000U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH              2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_1294
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1295_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH           2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK  0x00000F00U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH          4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH  9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_1296_READ_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK                           0x07000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET             0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET          0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_1296
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_1296
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1
+
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_MASK     0x07000000U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH             3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1297_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__REG DENALI_PHY_1297
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__FLD LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1
+
+#define LPDDR4__DENALI_PHY_1298_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__REG DENALI_PHY_1298
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__FLD LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1
+
+#define LPDDR4__DENALI_PHY_1299_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1
+
+#define LPDDR4__DENALI_PHY_1300_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_1300
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1
+
+#define LPDDR4__DENALI_PHY_1301_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_1301
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1
+
+#define LPDDR4__DENALI_PHY_1302_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_1302
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1
+
+#define LPDDR4__DENALI_PHY_1303_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_1303
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1
+
+#define LPDDR4__DENALI_PHY_1304_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_1304
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1
+
+#define LPDDR4__DENALI_PHY_1305_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_1305
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1
+
+#define LPDDR4__DENALI_PHY_1306_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_1306
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1
+
+#define LPDDR4__DENALI_PHY_1307_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_1307
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1
+
+#define LPDDR4__DENALI_PHY_1308_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1
+
+#define LPDDR4__DENALI_PHY_1309_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_WIDTH                    30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_1309
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1
+
+#define LPDDR4__DENALI_PHY_1310_READ_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK                           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH          10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_MASK             0x003F0000U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_WIDTH                     6U
+#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1
+
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_MASK             0x3F000000U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_WIDTH                     6U
+#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311_READ_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK                           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH             6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH             6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH           4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1312_READ_MASK                            0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK                           0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_MASK      0x00000003U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_WIDTH              2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH  1U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR  0U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET  0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1314_READ_MASK                            0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK                           0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_WIDTH               8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_MASK            0x00030000U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_WIDTH                    2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_MASK      0x3F000000U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_WIDTH              6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1
+
+#define LPDDR4__DENALI_PHY_1315_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_WIDTH         8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOSET             0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_1316_READ_MASK                            0x00003F01U
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK                           0x00003F01U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOSET                 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_ADR_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_MASK        0x00003F00U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH                6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1317_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_WIDTH                  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_MASK       0x00000700U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_WIDTH               3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_MASK           0x07FF0000U
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_WIDTH                  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_1318_READ_MASK                            0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK                           0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH          3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK     0x00001F00U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK  0x07FF0000U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1319_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK                           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1320_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1320
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1320
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1321_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1321
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1321
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1322_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1322
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1322
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1323_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK                           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1323
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_1323
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_1324_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK                           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_1325_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK                           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_1326_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK                           0x0000000FU
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_1326
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_1327_READ_MASK                            0x03FF010FU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK                           0x03FF010FU
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1328_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__REG DENALI_PHY_1328
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__REG DENALI_PHY_1328
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
new file mode 100644
index 0000000..abb7640
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1536_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1536_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH   11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1536
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET          0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1536
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH              3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1536
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_1537_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH             32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1537
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1538_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1538_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH        16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK  0x00FF0000U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH          8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH   4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1539_READ_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1539_WRITE_MASK                           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH         11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH         7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH        8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1540_READ_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_1540_WRITE_MASK                           0x01000707U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT       8U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH       3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET             0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1540
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOSET                  0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1541_READ_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1541_WRITE_MASK                           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_WIDTH                 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_MASK   0x00007F00U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_WIDTH           7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH            5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOSET              0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1542_READ_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_1542_WRITE_MASK                           0x01070301U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET    0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_MASK                 0x00000300U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_WIDTH                         2U
+#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK     0x00070000U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOSET                      0U
+#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_1543_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543_WRITE_MASK                           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_MASK             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_WIDTH                    27U
+#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1543
+#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_1544_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1544_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1544
+#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_1545_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_WIDTH                32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1545
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_1546_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH       32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1546
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_1547_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1547_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_MASK          0x000007FFU
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_WIDTH                 11U
+#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1547
+#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2
+
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH            11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1547
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2
+
+#define LPDDR4__DENALI_PHY_1548_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1548_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_WIDTH                   11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1548
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2
+
+#define LPDDR4__DENALI_PHY_1549_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1549
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_1550_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1550_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1550
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_MASK      0x03000000U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH              2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1550
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1551_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1551_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH           2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2
+
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK  0x00000F00U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH          4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH  9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_1552_READ_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_1552_WRITE_MASK                           0x07000001U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET             0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1552
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET          0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1552
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1552
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2
+
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_MASK     0x07000000U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1552
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1553_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__REG DENALI_PHY_1553
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__FLD LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1554_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__REG DENALI_PHY_1554
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__FLD LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1555_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1555
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2
+
+#define LPDDR4__DENALI_PHY_1556_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1556
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2
+
+#define LPDDR4__DENALI_PHY_1557_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1557
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2
+
+#define LPDDR4__DENALI_PHY_1558_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1558
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2
+
+#define LPDDR4__DENALI_PHY_1559_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1559
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2
+
+#define LPDDR4__DENALI_PHY_1560_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1560
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2
+
+#define LPDDR4__DENALI_PHY_1561_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1561
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2
+
+#define LPDDR4__DENALI_PHY_1562_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1562
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2
+
+#define LPDDR4__DENALI_PHY_1563_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1563
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2
+
+#define LPDDR4__DENALI_PHY_1564_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1564
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2
+
+#define LPDDR4__DENALI_PHY_1565_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_WIDTH                    30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1565
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2
+
+#define LPDDR4__DENALI_PHY_1566_READ_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1566_WRITE_MASK                           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH          10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_MASK             0x003F0000U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2
+
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_MASK             0x3F000000U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567_READ_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1567_WRITE_MASK                           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH           4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1568_READ_MASK                            0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1568_WRITE_MASK                           0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_MASK      0x00000003U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_WIDTH              2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1569_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH  1U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR  0U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET  0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1570_READ_MASK                            0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1570_WRITE_MASK                           0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_WIDTH               8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_MASK            0x00030000U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_WIDTH                    2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_MASK      0x3F000000U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_WIDTH              6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2
+
+#define LPDDR4__DENALI_PHY_1571_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1571_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_WIDTH         8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOSET             0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_1572_READ_MASK                            0x00003F01U
+#define LPDDR4__DENALI_PHY_1572_WRITE_MASK                           0x00003F01U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOSET                 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_2__REG DENALI_PHY_1572
+#define LPDDR4__PHY_ADR_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_MASK        0x00003F00U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH                6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1572
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1573_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1573_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_WIDTH                  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_MASK       0x00000700U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_WIDTH               3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_MASK           0x07FF0000U
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_WIDTH                  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_1574_READ_MASK                            0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1574_WRITE_MASK                           0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH          3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK     0x00001F00U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK  0x07FF0000U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1575_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1575_WRITE_MASK                           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1576_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1576_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1576
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1576
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1577_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1577_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1577
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1577
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1578_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1578_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1578
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1578
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1579_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1579_WRITE_MASK                           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1579
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1579
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_1580_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1580_WRITE_MASK                           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1581_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1581_WRITE_MASK                           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_1582_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1582_WRITE_MASK                           0x0000000FU
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1582
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1583_READ_MASK                            0x03FF010FU
+#define LPDDR4__DENALI_PHY_1583_WRITE_MASK                           0x03FF010FU
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_WIDTH           10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1584_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1584_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__REG DENALI_PHY_1584
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__REG DENALI_PHY_1584
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
new file mode 100644
index 0000000..22384a1
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[435];
+extern u32 g_lpddr4_pi_rw_mask[424];
+extern u32 g_lpddr4_data_slice_0_rw_mask[137];
+extern u32 g_lpddr4_data_slice_1_rw_mask[137];
+extern u32 g_lpddr4_data_slice_2_rw_mask[137];
+extern u32 g_lpddr4_data_slice_3_rw_mask[137];
+extern u32 g_lpddr4_address_slice_0_rw_mask[49];
+extern u32 g_lpddr4_address_slice_1_rw_mask[49];
+extern u32 g_lpddr4_address_slice_2_rw_mask[49];
+extern u32 g_lpddr4_phy_core_rw_mask[132];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
similarity index 90%
copy from drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
copy to drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
index 94202c9..102184a 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
@@ -2,22 +2,22 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#ifndef LPDDR4_16BIT_IF_H
-#define LPDDR4_16BIT_IF_H
+#ifndef LPDDR4_AM62A_IF_H
+#define LPDDR4_AM62A_IF_H
 
 #include <linux/types.h>
 
 #define LPDDR4_INTR_MAX_CS (2U)
 
-#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+#define LPDDR4_INTR_CTL_REG_COUNT (435U)
 
-#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (424U)
 
-#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
+#define LPDDR4_INTR_PHY_REG_COUNT (1924U)
 
 typedef enum {
 	LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT			= 0U,
@@ -105,4 +105,4 @@
 	LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT		= 28U
 } lpddr4_intr_phyindepinterrupt;
 
-#endif  /* LPDDR4_16BIT_IF_H */
+#endif  /* LPDDR4_AM62A_IF_H */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
new file mode 100644
index 0000000..4c41863
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM62A_OBJ_IF_H
+#define LPDDR4_AM62A_OBJ_IF_H
+
+#include "lpddr4_am62a_if.h"
+
+#endif  /* LPDDR4_AM62A_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
new file mode 100644
index 0000000..ab2b1f1
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM62A_STRUCTS_IF_H
+#define LPDDR4_AM62A_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_am62a_if.h"
+
+#endif  /* LPDDR4_AM62A_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
similarity index 80%
copy from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
copy to drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
index 4113608..7a9ec00 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_CTL_REGS_H_
@@ -16,6 +16,8 @@
 #include "lpddr4_data_slice_2_macros.h"
 #include "lpddr4_data_slice_3_macros.h"
 #include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_address_slice_1_macros.h"
+#include "lpddr4_address_slice_2_macros.h"
 #include "lpddr4_phy_core_macros.h"
 
 typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
@@ -454,31 +456,7 @@
 	volatile u32 DENALI_CTL_432;
 	volatile u32 DENALI_CTL_433;
 	volatile u32 DENALI_CTL_434;
-	volatile u32 DENALI_CTL_435;
-	volatile u32 DENALI_CTL_436;
-	volatile u32 DENALI_CTL_437;
-	volatile u32 DENALI_CTL_438;
-	volatile u32 DENALI_CTL_439;
-	volatile u32 DENALI_CTL_440;
-	volatile u32 DENALI_CTL_441;
-	volatile u32 DENALI_CTL_442;
-	volatile u32 DENALI_CTL_443;
-	volatile u32 DENALI_CTL_444;
-	volatile u32 DENALI_CTL_445;
-	volatile u32 DENALI_CTL_446;
-	volatile u32 DENALI_CTL_447;
-	volatile u32 DENALI_CTL_448;
-	volatile u32 DENALI_CTL_449;
-	volatile u32 DENALI_CTL_450;
-	volatile u32 DENALI_CTL_451;
-	volatile u32 DENALI_CTL_452;
-	volatile u32 DENALI_CTL_453;
-	volatile u32 DENALI_CTL_454;
-	volatile u32 DENALI_CTL_455;
-	volatile u32 DENALI_CTL_456;
-	volatile u32 DENALI_CTL_457;
-	volatile u32 DENALI_CTL_458;
-	volatile char pad__0[0x18D4U];
+	volatile char pad__0[0x1934U];
 	volatile u32 DENALI_PI_0;
 	volatile u32 DENALI_PI_1;
 	volatile u32 DENALI_PI_2;
@@ -779,7 +757,131 @@
 	volatile u32 DENALI_PI_297;
 	volatile u32 DENALI_PI_298;
 	volatile u32 DENALI_PI_299;
-	volatile char pad__1[0x1B50U];
+	volatile u32 DENALI_PI_300;
+	volatile u32 DENALI_PI_301;
+	volatile u32 DENALI_PI_302;
+	volatile u32 DENALI_PI_303;
+	volatile u32 DENALI_PI_304;
+	volatile u32 DENALI_PI_305;
+	volatile u32 DENALI_PI_306;
+	volatile u32 DENALI_PI_307;
+	volatile u32 DENALI_PI_308;
+	volatile u32 DENALI_PI_309;
+	volatile u32 DENALI_PI_310;
+	volatile u32 DENALI_PI_311;
+	volatile u32 DENALI_PI_312;
+	volatile u32 DENALI_PI_313;
+	volatile u32 DENALI_PI_314;
+	volatile u32 DENALI_PI_315;
+	volatile u32 DENALI_PI_316;
+	volatile u32 DENALI_PI_317;
+	volatile u32 DENALI_PI_318;
+	volatile u32 DENALI_PI_319;
+	volatile u32 DENALI_PI_320;
+	volatile u32 DENALI_PI_321;
+	volatile u32 DENALI_PI_322;
+	volatile u32 DENALI_PI_323;
+	volatile u32 DENALI_PI_324;
+	volatile u32 DENALI_PI_325;
+	volatile u32 DENALI_PI_326;
+	volatile u32 DENALI_PI_327;
+	volatile u32 DENALI_PI_328;
+	volatile u32 DENALI_PI_329;
+	volatile u32 DENALI_PI_330;
+	volatile u32 DENALI_PI_331;
+	volatile u32 DENALI_PI_332;
+	volatile u32 DENALI_PI_333;
+	volatile u32 DENALI_PI_334;
+	volatile u32 DENALI_PI_335;
+	volatile u32 DENALI_PI_336;
+	volatile u32 DENALI_PI_337;
+	volatile u32 DENALI_PI_338;
+	volatile u32 DENALI_PI_339;
+	volatile u32 DENALI_PI_340;
+	volatile u32 DENALI_PI_341;
+	volatile u32 DENALI_PI_342;
+	volatile u32 DENALI_PI_343;
+	volatile u32 DENALI_PI_344;
+	volatile u32 DENALI_PI_345;
+	volatile u32 DENALI_PI_346;
+	volatile u32 DENALI_PI_347;
+	volatile u32 DENALI_PI_348;
+	volatile u32 DENALI_PI_349;
+	volatile u32 DENALI_PI_350;
+	volatile u32 DENALI_PI_351;
+	volatile u32 DENALI_PI_352;
+	volatile u32 DENALI_PI_353;
+	volatile u32 DENALI_PI_354;
+	volatile u32 DENALI_PI_355;
+	volatile u32 DENALI_PI_356;
+	volatile u32 DENALI_PI_357;
+	volatile u32 DENALI_PI_358;
+	volatile u32 DENALI_PI_359;
+	volatile u32 DENALI_PI_360;
+	volatile u32 DENALI_PI_361;
+	volatile u32 DENALI_PI_362;
+	volatile u32 DENALI_PI_363;
+	volatile u32 DENALI_PI_364;
+	volatile u32 DENALI_PI_365;
+	volatile u32 DENALI_PI_366;
+	volatile u32 DENALI_PI_367;
+	volatile u32 DENALI_PI_368;
+	volatile u32 DENALI_PI_369;
+	volatile u32 DENALI_PI_370;
+	volatile u32 DENALI_PI_371;
+	volatile u32 DENALI_PI_372;
+	volatile u32 DENALI_PI_373;
+	volatile u32 DENALI_PI_374;
+	volatile u32 DENALI_PI_375;
+	volatile u32 DENALI_PI_376;
+	volatile u32 DENALI_PI_377;
+	volatile u32 DENALI_PI_378;
+	volatile u32 DENALI_PI_379;
+	volatile u32 DENALI_PI_380;
+	volatile u32 DENALI_PI_381;
+	volatile u32 DENALI_PI_382;
+	volatile u32 DENALI_PI_383;
+	volatile u32 DENALI_PI_384;
+	volatile u32 DENALI_PI_385;
+	volatile u32 DENALI_PI_386;
+	volatile u32 DENALI_PI_387;
+	volatile u32 DENALI_PI_388;
+	volatile u32 DENALI_PI_389;
+	volatile u32 DENALI_PI_390;
+	volatile u32 DENALI_PI_391;
+	volatile u32 DENALI_PI_392;
+	volatile u32 DENALI_PI_393;
+	volatile u32 DENALI_PI_394;
+	volatile u32 DENALI_PI_395;
+	volatile u32 DENALI_PI_396;
+	volatile u32 DENALI_PI_397;
+	volatile u32 DENALI_PI_398;
+	volatile u32 DENALI_PI_399;
+	volatile u32 DENALI_PI_400;
+	volatile u32 DENALI_PI_401;
+	volatile u32 DENALI_PI_402;
+	volatile u32 DENALI_PI_403;
+	volatile u32 DENALI_PI_404;
+	volatile u32 DENALI_PI_405;
+	volatile u32 DENALI_PI_406;
+	volatile u32 DENALI_PI_407;
+	volatile u32 DENALI_PI_408;
+	volatile u32 DENALI_PI_409;
+	volatile u32 DENALI_PI_410;
+	volatile u32 DENALI_PI_411;
+	volatile u32 DENALI_PI_412;
+	volatile u32 DENALI_PI_413;
+	volatile u32 DENALI_PI_414;
+	volatile u32 DENALI_PI_415;
+	volatile u32 DENALI_PI_416;
+	volatile u32 DENALI_PI_417;
+	volatile u32 DENALI_PI_418;
+	volatile u32 DENALI_PI_419;
+	volatile u32 DENALI_PI_420;
+	volatile u32 DENALI_PI_421;
+	volatile u32 DENALI_PI_422;
+	volatile u32 DENALI_PI_423;
+	volatile char pad__1[0x1960U];
 	volatile u32 DENALI_PHY_0;
 	volatile u32 DENALI_PHY_1;
 	volatile u32 DENALI_PHY_2;
@@ -917,10 +1019,7 @@
 	volatile u32 DENALI_PHY_134;
 	volatile u32 DENALI_PHY_135;
 	volatile u32 DENALI_PHY_136;
-	volatile u32 DENALI_PHY_137;
-	volatile u32 DENALI_PHY_138;
-	volatile u32 DENALI_PHY_139;
-	volatile char pad__2[0x1D0U];
+	volatile char pad__2[0x1DCU];
 	volatile u32 DENALI_PHY_256;
 	volatile u32 DENALI_PHY_257;
 	volatile u32 DENALI_PHY_258;
@@ -1058,10 +1157,7 @@
 	volatile u32 DENALI_PHY_390;
 	volatile u32 DENALI_PHY_391;
 	volatile u32 DENALI_PHY_392;
-	volatile u32 DENALI_PHY_393;
-	volatile u32 DENALI_PHY_394;
-	volatile u32 DENALI_PHY_395;
-	volatile char pad__3[0x1D0U];
+	volatile char pad__3[0x1DCU];
 	volatile u32 DENALI_PHY_512;
 	volatile u32 DENALI_PHY_513;
 	volatile u32 DENALI_PHY_514;
@@ -1199,10 +1295,7 @@
 	volatile u32 DENALI_PHY_646;
 	volatile u32 DENALI_PHY_647;
 	volatile u32 DENALI_PHY_648;
-	volatile u32 DENALI_PHY_649;
-	volatile u32 DENALI_PHY_650;
-	volatile u32 DENALI_PHY_651;
-	volatile char pad__4[0x1D0U];
+	volatile char pad__4[0x1DCU];
 	volatile u32 DENALI_PHY_768;
 	volatile u32 DENALI_PHY_769;
 	volatile u32 DENALI_PHY_770;
@@ -1340,10 +1433,7 @@
 	volatile u32 DENALI_PHY_902;
 	volatile u32 DENALI_PHY_903;
 	volatile u32 DENALI_PHY_904;
-	volatile u32 DENALI_PHY_905;
-	volatile u32 DENALI_PHY_906;
-	volatile u32 DENALI_PHY_907;
-	volatile char pad__5[0x1D0U];
+	volatile char pad__5[0x1DCU];
 	volatile u32 DENALI_PHY_1024;
 	volatile u32 DENALI_PHY_1025;
 	volatile u32 DENALI_PHY_1026;
@@ -1393,10 +1483,7 @@
 	volatile u32 DENALI_PHY_1070;
 	volatile u32 DENALI_PHY_1071;
 	volatile u32 DENALI_PHY_1072;
-	volatile u32 DENALI_PHY_1073;
-	volatile u32 DENALI_PHY_1074;
-	volatile u32 DENALI_PHY_1075;
-	volatile char pad__6[0x330U];
+	volatile char pad__6[0x33CU];
 	volatile u32 DENALI_PHY_1280;
 	volatile u32 DENALI_PHY_1281;
 	volatile u32 DENALI_PHY_1282;
@@ -1446,100 +1533,189 @@
 	volatile u32 DENALI_PHY_1326;
 	volatile u32 DENALI_PHY_1327;
 	volatile u32 DENALI_PHY_1328;
-	volatile u32 DENALI_PHY_1329;
-	volatile u32 DENALI_PHY_1330;
-	volatile u32 DENALI_PHY_1331;
-	volatile u32 DENALI_PHY_1332;
-	volatile u32 DENALI_PHY_1333;
-	volatile u32 DENALI_PHY_1334;
-	volatile u32 DENALI_PHY_1335;
-	volatile u32 DENALI_PHY_1336;
-	volatile u32 DENALI_PHY_1337;
-	volatile u32 DENALI_PHY_1338;
-	volatile u32 DENALI_PHY_1339;
-	volatile u32 DENALI_PHY_1340;
-	volatile u32 DENALI_PHY_1341;
-	volatile u32 DENALI_PHY_1342;
-	volatile u32 DENALI_PHY_1343;
-	volatile u32 DENALI_PHY_1344;
-	volatile u32 DENALI_PHY_1345;
-	volatile u32 DENALI_PHY_1346;
-	volatile u32 DENALI_PHY_1347;
-	volatile u32 DENALI_PHY_1348;
-	volatile u32 DENALI_PHY_1349;
-	volatile u32 DENALI_PHY_1350;
-	volatile u32 DENALI_PHY_1351;
-	volatile u32 DENALI_PHY_1352;
-	volatile u32 DENALI_PHY_1353;
-	volatile u32 DENALI_PHY_1354;
-	volatile u32 DENALI_PHY_1355;
-	volatile u32 DENALI_PHY_1356;
-	volatile u32 DENALI_PHY_1357;
-	volatile u32 DENALI_PHY_1358;
-	volatile u32 DENALI_PHY_1359;
-	volatile u32 DENALI_PHY_1360;
-	volatile u32 DENALI_PHY_1361;
-	volatile u32 DENALI_PHY_1362;
-	volatile u32 DENALI_PHY_1363;
-	volatile u32 DENALI_PHY_1364;
-	volatile u32 DENALI_PHY_1365;
-	volatile u32 DENALI_PHY_1366;
-	volatile u32 DENALI_PHY_1367;
-	volatile u32 DENALI_PHY_1368;
-	volatile u32 DENALI_PHY_1369;
-	volatile u32 DENALI_PHY_1370;
-	volatile u32 DENALI_PHY_1371;
-	volatile u32 DENALI_PHY_1372;
-	volatile u32 DENALI_PHY_1373;
-	volatile u32 DENALI_PHY_1374;
-	volatile u32 DENALI_PHY_1375;
-	volatile u32 DENALI_PHY_1376;
-	volatile u32 DENALI_PHY_1377;
-	volatile u32 DENALI_PHY_1378;
-	volatile u32 DENALI_PHY_1379;
-	volatile u32 DENALI_PHY_1380;
-	volatile u32 DENALI_PHY_1381;
-	volatile u32 DENALI_PHY_1382;
-	volatile u32 DENALI_PHY_1383;
-	volatile u32 DENALI_PHY_1384;
-	volatile u32 DENALI_PHY_1385;
-	volatile u32 DENALI_PHY_1386;
-	volatile u32 DENALI_PHY_1387;
-	volatile u32 DENALI_PHY_1388;
-	volatile u32 DENALI_PHY_1389;
-	volatile u32 DENALI_PHY_1390;
-	volatile u32 DENALI_PHY_1391;
-	volatile u32 DENALI_PHY_1392;
-	volatile u32 DENALI_PHY_1393;
-	volatile u32 DENALI_PHY_1394;
-	volatile u32 DENALI_PHY_1395;
-	volatile u32 DENALI_PHY_1396;
-	volatile u32 DENALI_PHY_1397;
-	volatile u32 DENALI_PHY_1398;
-	volatile u32 DENALI_PHY_1399;
-	volatile u32 DENALI_PHY_1400;
-	volatile u32 DENALI_PHY_1401;
-	volatile u32 DENALI_PHY_1402;
-	volatile u32 DENALI_PHY_1403;
-	volatile u32 DENALI_PHY_1404;
-	volatile u32 DENALI_PHY_1405;
-	volatile u32 DENALI_PHY_1406;
-	volatile u32 DENALI_PHY_1407;
-	volatile u32 DENALI_PHY_1408;
-	volatile u32 DENALI_PHY_1409;
-	volatile u32 DENALI_PHY_1410;
-	volatile u32 DENALI_PHY_1411;
-	volatile u32 DENALI_PHY_1412;
-	volatile u32 DENALI_PHY_1413;
-	volatile u32 DENALI_PHY_1414;
-	volatile u32 DENALI_PHY_1415;
-	volatile u32 DENALI_PHY_1416;
-	volatile u32 DENALI_PHY_1417;
-	volatile u32 DENALI_PHY_1418;
-	volatile u32 DENALI_PHY_1419;
-	volatile u32 DENALI_PHY_1420;
-	volatile u32 DENALI_PHY_1421;
-	volatile u32 DENALI_PHY_1422;
+	volatile char pad__7[0x33CU];
+	volatile u32 DENALI_PHY_1536;
+	volatile u32 DENALI_PHY_1537;
+	volatile u32 DENALI_PHY_1538;
+	volatile u32 DENALI_PHY_1539;
+	volatile u32 DENALI_PHY_1540;
+	volatile u32 DENALI_PHY_1541;
+	volatile u32 DENALI_PHY_1542;
+	volatile u32 DENALI_PHY_1543;
+	volatile u32 DENALI_PHY_1544;
+	volatile u32 DENALI_PHY_1545;
+	volatile u32 DENALI_PHY_1546;
+	volatile u32 DENALI_PHY_1547;
+	volatile u32 DENALI_PHY_1548;
+	volatile u32 DENALI_PHY_1549;
+	volatile u32 DENALI_PHY_1550;
+	volatile u32 DENALI_PHY_1551;
+	volatile u32 DENALI_PHY_1552;
+	volatile u32 DENALI_PHY_1553;
+	volatile u32 DENALI_PHY_1554;
+	volatile u32 DENALI_PHY_1555;
+	volatile u32 DENALI_PHY_1556;
+	volatile u32 DENALI_PHY_1557;
+	volatile u32 DENALI_PHY_1558;
+	volatile u32 DENALI_PHY_1559;
+	volatile u32 DENALI_PHY_1560;
+	volatile u32 DENALI_PHY_1561;
+	volatile u32 DENALI_PHY_1562;
+	volatile u32 DENALI_PHY_1563;
+	volatile u32 DENALI_PHY_1564;
+	volatile u32 DENALI_PHY_1565;
+	volatile u32 DENALI_PHY_1566;
+	volatile u32 DENALI_PHY_1567;
+	volatile u32 DENALI_PHY_1568;
+	volatile u32 DENALI_PHY_1569;
+	volatile u32 DENALI_PHY_1570;
+	volatile u32 DENALI_PHY_1571;
+	volatile u32 DENALI_PHY_1572;
+	volatile u32 DENALI_PHY_1573;
+	volatile u32 DENALI_PHY_1574;
+	volatile u32 DENALI_PHY_1575;
+	volatile u32 DENALI_PHY_1576;
+	volatile u32 DENALI_PHY_1577;
+	volatile u32 DENALI_PHY_1578;
+	volatile u32 DENALI_PHY_1579;
+	volatile u32 DENALI_PHY_1580;
+	volatile u32 DENALI_PHY_1581;
+	volatile u32 DENALI_PHY_1582;
+	volatile u32 DENALI_PHY_1583;
+	volatile u32 DENALI_PHY_1584;
+	volatile char pad__8[0x33CU];
+	volatile u32 DENALI_PHY_1792;
+	volatile u32 DENALI_PHY_1793;
+	volatile u32 DENALI_PHY_1794;
+	volatile u32 DENALI_PHY_1795;
+	volatile u32 DENALI_PHY_1796;
+	volatile u32 DENALI_PHY_1797;
+	volatile u32 DENALI_PHY_1798;
+	volatile u32 DENALI_PHY_1799;
+	volatile u32 DENALI_PHY_1800;
+	volatile u32 DENALI_PHY_1801;
+	volatile u32 DENALI_PHY_1802;
+	volatile u32 DENALI_PHY_1803;
+	volatile u32 DENALI_PHY_1804;
+	volatile u32 DENALI_PHY_1805;
+	volatile u32 DENALI_PHY_1806;
+	volatile u32 DENALI_PHY_1807;
+	volatile u32 DENALI_PHY_1808;
+	volatile u32 DENALI_PHY_1809;
+	volatile u32 DENALI_PHY_1810;
+	volatile u32 DENALI_PHY_1811;
+	volatile u32 DENALI_PHY_1812;
+	volatile u32 DENALI_PHY_1813;
+	volatile u32 DENALI_PHY_1814;
+	volatile u32 DENALI_PHY_1815;
+	volatile u32 DENALI_PHY_1816;
+	volatile u32 DENALI_PHY_1817;
+	volatile u32 DENALI_PHY_1818;
+	volatile u32 DENALI_PHY_1819;
+	volatile u32 DENALI_PHY_1820;
+	volatile u32 DENALI_PHY_1821;
+	volatile u32 DENALI_PHY_1822;
+	volatile u32 DENALI_PHY_1823;
+	volatile u32 DENALI_PHY_1824;
+	volatile u32 DENALI_PHY_1825;
+	volatile u32 DENALI_PHY_1826;
+	volatile u32 DENALI_PHY_1827;
+	volatile u32 DENALI_PHY_1828;
+	volatile u32 DENALI_PHY_1829;
+	volatile u32 DENALI_PHY_1830;
+	volatile u32 DENALI_PHY_1831;
+	volatile u32 DENALI_PHY_1832;
+	volatile u32 DENALI_PHY_1833;
+	volatile u32 DENALI_PHY_1834;
+	volatile u32 DENALI_PHY_1835;
+	volatile u32 DENALI_PHY_1836;
+	volatile u32 DENALI_PHY_1837;
+	volatile u32 DENALI_PHY_1838;
+	volatile u32 DENALI_PHY_1839;
+	volatile u32 DENALI_PHY_1840;
+	volatile u32 DENALI_PHY_1841;
+	volatile u32 DENALI_PHY_1842;
+	volatile u32 DENALI_PHY_1843;
+	volatile u32 DENALI_PHY_1844;
+	volatile u32 DENALI_PHY_1845;
+	volatile u32 DENALI_PHY_1846;
+	volatile u32 DENALI_PHY_1847;
+	volatile u32 DENALI_PHY_1848;
+	volatile u32 DENALI_PHY_1849;
+	volatile u32 DENALI_PHY_1850;
+	volatile u32 DENALI_PHY_1851;
+	volatile u32 DENALI_PHY_1852;
+	volatile u32 DENALI_PHY_1853;
+	volatile u32 DENALI_PHY_1854;
+	volatile u32 DENALI_PHY_1855;
+	volatile u32 DENALI_PHY_1856;
+	volatile u32 DENALI_PHY_1857;
+	volatile u32 DENALI_PHY_1858;
+	volatile u32 DENALI_PHY_1859;
+	volatile u32 DENALI_PHY_1860;
+	volatile u32 DENALI_PHY_1861;
+	volatile u32 DENALI_PHY_1862;
+	volatile u32 DENALI_PHY_1863;
+	volatile u32 DENALI_PHY_1864;
+	volatile u32 DENALI_PHY_1865;
+	volatile u32 DENALI_PHY_1866;
+	volatile u32 DENALI_PHY_1867;
+	volatile u32 DENALI_PHY_1868;
+	volatile u32 DENALI_PHY_1869;
+	volatile u32 DENALI_PHY_1870;
+	volatile u32 DENALI_PHY_1871;
+	volatile u32 DENALI_PHY_1872;
+	volatile u32 DENALI_PHY_1873;
+	volatile u32 DENALI_PHY_1874;
+	volatile u32 DENALI_PHY_1875;
+	volatile u32 DENALI_PHY_1876;
+	volatile u32 DENALI_PHY_1877;
+	volatile u32 DENALI_PHY_1878;
+	volatile u32 DENALI_PHY_1879;
+	volatile u32 DENALI_PHY_1880;
+	volatile u32 DENALI_PHY_1881;
+	volatile u32 DENALI_PHY_1882;
+	volatile u32 DENALI_PHY_1883;
+	volatile u32 DENALI_PHY_1884;
+	volatile u32 DENALI_PHY_1885;
+	volatile u32 DENALI_PHY_1886;
+	volatile u32 DENALI_PHY_1887;
+	volatile u32 DENALI_PHY_1888;
+	volatile u32 DENALI_PHY_1889;
+	volatile u32 DENALI_PHY_1890;
+	volatile u32 DENALI_PHY_1891;
+	volatile u32 DENALI_PHY_1892;
+	volatile u32 DENALI_PHY_1893;
+	volatile u32 DENALI_PHY_1894;
+	volatile u32 DENALI_PHY_1895;
+	volatile u32 DENALI_PHY_1896;
+	volatile u32 DENALI_PHY_1897;
+	volatile u32 DENALI_PHY_1898;
+	volatile u32 DENALI_PHY_1899;
+	volatile u32 DENALI_PHY_1900;
+	volatile u32 DENALI_PHY_1901;
+	volatile u32 DENALI_PHY_1902;
+	volatile u32 DENALI_PHY_1903;
+	volatile u32 DENALI_PHY_1904;
+	volatile u32 DENALI_PHY_1905;
+	volatile u32 DENALI_PHY_1906;
+	volatile u32 DENALI_PHY_1907;
+	volatile u32 DENALI_PHY_1908;
+	volatile u32 DENALI_PHY_1909;
+	volatile u32 DENALI_PHY_1910;
+	volatile u32 DENALI_PHY_1911;
+	volatile u32 DENALI_PHY_1912;
+	volatile u32 DENALI_PHY_1913;
+	volatile u32 DENALI_PHY_1914;
+	volatile u32 DENALI_PHY_1915;
+	volatile u32 DENALI_PHY_1916;
+	volatile u32 DENALI_PHY_1917;
+	volatile u32 DENALI_PHY_1918;
+	volatile u32 DENALI_PHY_1919;
+	volatile u32 DENALI_PHY_1920;
+	volatile u32 DENALI_PHY_1921;
+	volatile u32 DENALI_PHY_1922;
+	volatile u32 DENALI_PHY_1923;
 } lpddr4_ctlregs;
 
 #endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
new file mode 100644
index 0000000..013f1f0
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK                               0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK                              0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK    0x00000007U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH            3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK  0x00007F00U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH          7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK   0x07FF0000U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK                               0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK                              0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK  0x0000000FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH          4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH       10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH           3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK                               0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK                              0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK     0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH             2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET                 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK                               0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK                              0x01030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK               0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH                       6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK              0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH                      4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH                     2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT       24U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET        0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK                               0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK                              0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET               0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH           2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH              5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK                               0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK                              0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH                4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT       8U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH       4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH        2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK   0x1F000000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH           5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK                               0x0101FF03U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK                              0x0101FF03U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK                0x00000003U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH                        2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK                0x0001FF00U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH                        9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET                 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK                               0x00000001U
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK                              0x00000001U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET             0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH        32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK     0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH            28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK                              0x7F0101FFU
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_MASK                    0x000001FFU
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_SHIFT                            0U
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_WIDTH                            9U
+#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOSET                        0U
+#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_WIDTH                 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK                              0x010101FFU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_MASK          0x000001FFU
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_WIDTH                  9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET            0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT      24U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH       1U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR       0U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET       0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK                              0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH              6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_MASK             0x00007F00U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_WIDTH                     7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK                              0x01FF000FU
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_MASK           0x00000100U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOSET                   0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_15
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK                              0x01FF0701U
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_MASK                      0x00000001U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_SHIFT                              0U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WIDTH                              1U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOCLR                              0U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOSET                              0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_16__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_MASK                  0x00000700U
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_WIDTH                          3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_MASK          0x00000003U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_WIDTH                  2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_17
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK                              0x00000301U
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOSET                     0U
+#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_MASK              0x00000300U
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_WIDTH                      2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK                              0x070F0107U
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK      0x00000007U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH              3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK    0x00000100U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET            0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH         4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_MASK        0x07000000U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH                3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_WIDTH                  4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK                              0x3F030001U
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOSET                     0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_30
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_MASK                 0x00030000U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_WIDTH                         2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK                              0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_WIDTH                            8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_MASK          0x0000003FU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_MASK              0x00030000U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_WIDTH                      2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH          5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_WIDTH                    8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_MASK         0x03FFFF00U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH                18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK                              0x00073FFFU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_WIDTH                   6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_WIDTH                        3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK                              0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH   11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH             4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH         8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH                8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0
+
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_MASK         0x000F0000U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH                 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET         0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_36
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_WIDTH                 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_WIDTH                        16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOSET                     0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_MASK        0x000003FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_WIDTH               10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_MASK       0x03FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH              10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK   0x03FF0000U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK                              0x00FF0001U
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET           0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_WIDTH                    6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_45
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_WIDTH                       8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_WIDTH                   32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK                              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_MASK       0x0000FFFFU
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH              16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_MASK        0x07FF0000U
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK                              0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK       0x0000007FU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH               7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_MASK        0x00FF0000U
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH                8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK                              0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH        11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK                              0x0007FFFFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH          8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH           8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_WIDTH                       3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK      0x000003FFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_WIDTH                  21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_WIDTH                   16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0
+
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK      0x3FFF0000U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK                              0x00003FFFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK      0x00003FFFU
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_WIDTH                  18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH     2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_WIDTH                  32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH               32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK                              0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_MASK                   0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_WIDTH                          31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK                              0x0000003FU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_WIDTH                           6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_WIDTH                      32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH             32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH            8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOSET                 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK                  0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH                         18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK                              0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK                             0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_WIDTH                    11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_MASK         0x001F0000U
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_WIDTH                 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK                              0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK                             0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_MASK        0x000000FFU
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH                8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_WIDTH                     2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_MASK       0x003F0000U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_WIDTH               6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK  0xFF000000U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH          8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK                              0x010101FFU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK     0x000000FFU
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOSET               0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOSET                  0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK                              0x01010703U
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK                             0x01010703U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_MASK            0x00000003U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_WIDTH                    2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_MASK              0x00000700U
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_WIDTH                      3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET          0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOSET                0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK                              0x00000101U
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET        0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET              0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK                              0x07FFFF07U
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_MASK             0x00000007U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_WIDTH                     3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_WIDTH                    16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_MASK            0x07000000U
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_WIDTH                    3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK                              0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_WIDTH                   16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_WIDTH                   2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_MASK   0x7F000000U
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK                              0xFF01037FU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_MASK    0x0000007FU
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH            7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_MASK         0x00000300U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_WIDTH                 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOSET                       0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH                  8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_MASK              0x000007FFU
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_MASK               0x07FF0000U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_WIDTH                      11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK                              0x0103FFFFU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_MASK             0x000000FFU
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_WIDTH                     8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_WIDTH                    10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET               0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK                              0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_MASK    0x0000003FU
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH            6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_WIDTH                        4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_MASK                 0x001F0000U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_WIDTH                         5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_WIDTH                      5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK                              0x007F1F1FU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_WIDTH                    5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_MASK          0x007F0000U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_WIDTH                  7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK                              0x1F0703FFU
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_WIDTH                  10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_MASK            0x00070000U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_WIDTH                    3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK                              0x00000007U
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK                             0x00000007U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_MASK        0x00000007U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH                3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK                              0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_WIDTH                4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_MASK           0x00FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_WIDTH                   8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_WIDTH                 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_MASK           0x0FFF0000U
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK                              0x03FFFF01U
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOSET                 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_MASK               0x0000FF00U
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_MASK           0x03000000U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_WIDTH                   2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK                              0x1F010303U
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK                             0x1F010303U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_MASK                    0x00000003U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_SHIFT                            0U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_WIDTH                            2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_MASK                   0x00000300U
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_WIDTH                           2U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOSET                       0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK       0x1F000000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH               5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK                              0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK  0x0000001FU
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH          5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_MASK         0x00001F00U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH                 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_MASK           0x001F0000U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_WIDTH                   5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK                            0x00030703U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK                            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT      24U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK                             0x001F7F7FU
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK                            0x001F7F7FU
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_MASK      0x00007F00U
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_128_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_128_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_129_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_129_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_130_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_130_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_131_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_131_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_132_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_132_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_132
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_133_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_133_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_134_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_135_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_136_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_136_WRITE_MASK                            0x0003033FU
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_WIDTH                            2U
+#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_WIDTH                           2U
+#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
new file mode 100644
index 0000000..c107112
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK                             0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK                            0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH        7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK                             0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK                            0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT      8U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK                            0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK                            0x01030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH                     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH                   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK                            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT         8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT      24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK                            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT     8U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT     16U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK                            0x0101FF03U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH                      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH                      9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK                            0x7F0101FFU
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_WIDTH                           9U
+#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOSET                       0U
+#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_MASK        0x7F000000U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_WIDTH                7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_WIDTH                 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK                            0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_MASK            0x00007F00U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_WIDTH                    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK                            0x01FF000FU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOSET                  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_271
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK                            0x01FF0701U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_MASK                     0x00000001U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_SHIFT                             0U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOSET                             0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_272__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_MASK                 0x00000700U
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_WIDTH                         3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_WIDTH                 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_273
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK                            0x00000301U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOSET                    0U
+#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_WIDTH                     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK                            0x070F0107U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_WIDTH                 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK                            0x3F030001U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOSET                    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOSET                 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_286
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_WIDTH                        2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK                            0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_WIDTH                           8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_WIDTH                     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_WIDTH                   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_MASK        0x03FFFF00U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH               18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK                            0x00073FFFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_MASK          0x00003F00U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_WIDTH                  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_WIDTH                       3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK                            0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT   0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK      0x000F0000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK    0x0F000000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH               8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1
+
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH        1U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR        0U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_292
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_WIDTH                9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_WIDTH                       16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOSET                    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK                            0x00FF0001U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_WIDTH                   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_301
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_WIDTH                      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_WIDTH                  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK                            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK                            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_WIDTH                      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_MASK          0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_WIDTH                 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_WIDTH                  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1
+
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_WIDTH                 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_WIDTH                 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_WIDTH                         31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_WIDTH                          6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_WIDTH                     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOSET                0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH                        18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH                       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK                             0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK                            0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_WIDTH                   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_WIDTH                5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK                             0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK                            0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_MASK       0x000000FFU
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_MASK            0x00000300U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_WIDTH                    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_MASK      0x003F0000U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOSET                 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK                             0x01010703U
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK                            0x01010703U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_MASK           0x00000003U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_WIDTH                   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_MASK             0x00000700U
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_WIDTH                     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH         1U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR         0U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH       1U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR       0U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK                            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_WIDTH                    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_WIDTH                   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_WIDTH                   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK                            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_WIDTH                  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_WIDTH                  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_SHIFT         24U
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK                            0xFF01037FU
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_WIDTH                2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOSET                      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH                 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_WIDTH                    11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_WIDTH                    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_WIDTH                   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK                            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_WIDTH                       4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_WIDTH                        5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK                            0x007F1F1FU
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_WIDTH                    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_WIDTH                   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_WIDTH                 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK                            0x1F0703FFU
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_WIDTH                 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_MASK           0x00070000U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_WIDTH                   3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_WIDTH                    5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_MASK       0x00000007U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_WIDTH                  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_WIDTH                16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_WIDTH                 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK                            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOSET                0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_WIDTH                  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK                             0x1F010303U
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK                            0x1F010303U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_WIDTH                           2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_WIDTH                          2U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOSET                      0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH              5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_MASK        0x00001F00U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH                5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_MASK          0x001F0000U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_WIDTH                  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK                            0x00030703U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK                            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT      24U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK                             0x001F7F7FU
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK                            0x001F7F7FU
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_MASK      0x00007F00U
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_384_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_384_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_385_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_385_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_386_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_386_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_387_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_387_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_388_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_388_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_388
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_389_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_389_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_390_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_391_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_392_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_392_WRITE_MASK                            0x0003033FU
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_WIDTH                            2U
+#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_WIDTH                           2U
+#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
new file mode 100644
index 0000000..b8fb80e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK                             0x07FF7F07U
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK                            0x07FF7F07U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_WIDTH        7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK                             0x0703FF0FU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK                            0x0703FF0FU
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT      8U
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK                            0x010303FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT     0U
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK                            0x01030F3FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH                     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH                    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH                   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT     24U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH      1U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR      0U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK                            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT      24U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK                            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT     8U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT     16U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK                            0x0101FF03U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH                      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH                      9U
+#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOSET           0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__REG DENALI_PHY_521
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__FLD LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_522
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_523
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK                            0x7F0101FFU
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_WIDTH                           9U
+#define LPDDR4__PHY_DQ_IDLE_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_DQ_IDLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOSET                       0U
+#define LPDDR4__PHY_PDA_MODE_EN_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_PDA_MODE_EN_2__FLD LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_MASK        0x7F000000U
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_SHIFT               24U
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_WIDTH                7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_WIDTH                 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT     24U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH      1U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR      0U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK                            0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_MASK            0x00007F00U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_WIDTH                    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT      16U
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK                            0x01FF000FU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_527
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2
+
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOSET                  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_527
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_527
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK                            0x01FF0701U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_MASK                     0x00000001U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_SHIFT                             0U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOSET                             0U
+#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_528__PHY_LPDDR_2
+
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_MASK                 0x00000700U
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_WIDTH                         3U
+#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2
+
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_WIDTH                 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_529
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_WIDTH                32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_530
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK                            0x00000301U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOSET                    0U
+#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_531
+#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_WIDTH                     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_531
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_532
+#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_533
+#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_534
+#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_535
+#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_536
+#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_537
+#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK                            0x070F0107U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_WIDTH                 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK                            0x3F030001U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOSET                    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOSET                 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_542
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_WIDTH                        2U
+#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_WIDTH                 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK                            0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_WIDTH                           8U
+#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_WIDTH                 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_WIDTH                 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_WIDTH                     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_WIDTH                   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2
+
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_MASK        0x03FFFF00U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_WIDTH               18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK                            0x00073FFFU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT       0U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
+
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_MASK          0x00003F00U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_WIDTH                  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2
+
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_WIDTH                       3U
+#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK                            0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT   0U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK      0x000F0000U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK    0x0F000000U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_WIDTH               8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2
+
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_SHIFT               16U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH        1U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR        0U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_548
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_WIDTH                9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_549
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_550
+#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_551
+#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_552
+#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_553
+#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_WIDTH                       16U
+#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2
+
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOSET                    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2
+
+#define LPDDR4__DENALI_PHY_555_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_555_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_556_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_556_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_556
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2
+
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_556
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2
+
+#define LPDDR4__DENALI_PHY_557_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_557_WRITE_MASK                            0x00FF0001U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2
+
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_WIDTH                   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_557
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_WIDTH                      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2
+
+#define LPDDR4__DENALI_PHY_558_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_WIDTH                  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_559_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_559_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_560_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_560_WRITE_MASK                            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_561_WRITE_MASK                            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_562_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_WIDTH                      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_563_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_564_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_MASK          0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_WIDTH                 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_564
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_565_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_565_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_566_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_566_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_WIDTH                  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_566
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2
+
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_566
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_567_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_567_WRITE_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_567
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_568_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_WIDTH                 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_568
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_569_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_569_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_569
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_569
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_570_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_570_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_570
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
+
+#define LPDDR4__DENALI_PHY_571_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_WIDTH                 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_571
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_572_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_572_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_572
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_572
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_573_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_WIDTH                32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_573
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_574_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_574
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2
+
+#define LPDDR4__DENALI_PHY_575_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_WIDTH                         31U
+#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_575
+#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_576_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_576_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_WIDTH                          6U
+#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_576
+#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_577_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_WIDTH                     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_577
+#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_578_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_578
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_579_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOSET                0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
+
+#define LPDDR4__DENALI_PHY_580_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
+
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
+
+#define LPDDR4__DENALI_PHY_581_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
+
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
+
+#define LPDDR4__DENALI_PHY_582_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
+
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
+
+#define LPDDR4__DENALI_PHY_583_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_583_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
+#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
+
+#define LPDDR4__DENALI_PHY_584_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH                        18U
+#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
+#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
+
+#define LPDDR4__DENALI_PHY_585_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
+
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH                       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
+
+#define LPDDR4__DENALI_PHY_586_READ_MASK                             0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_586_WRITE_MASK                            0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_WIDTH                   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2
+
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_SHIFT               16U
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_WIDTH                5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_587_READ_MASK                             0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_587_WRITE_MASK                            0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_MASK       0x000000FFU
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_MASK            0x00000300U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_WIDTH                    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_MASK      0x003F0000U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2
+
+#define LPDDR4__DENALI_PHY_588_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_588_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOSET                 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_589_READ_MASK                             0x01010703U
+#define LPDDR4__DENALI_PHY_589_WRITE_MASK                            0x01010703U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_MASK           0x00000003U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_WIDTH                   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_MASK             0x00000700U
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_WIDTH                     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH         1U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR         0U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_590_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_590_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT       0U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH       1U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR       0U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_591_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_591_WRITE_MASK                            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_WIDTH                    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_WIDTH                   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_WIDTH                   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_592_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_592_WRITE_MASK                            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_WIDTH                  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_WIDTH                  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2
+
+#define LPDDR4__DENALI_PHY_593_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_593_WRITE_MASK                            0xFF01037FU
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_WIDTH                2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOSET                      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH                 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2
+
+#define LPDDR4__DENALI_PHY_594_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_594_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_WIDTH                    11U
+#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_594
+#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2
+
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_594
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2
+
+#define LPDDR4__DENALI_PHY_595_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_595_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_WIDTH                    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2
+
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_WIDTH                   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_596_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_596_WRITE_MASK                            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_WIDTH                       4U
+#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_WIDTH                        5U
+#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2
+
+#define LPDDR4__DENALI_PHY_597_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_597_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2
+
+#define LPDDR4__DENALI_PHY_598_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_598_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599_READ_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_599_WRITE_MASK                            0x007F1F1FU
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_WIDTH                    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_WIDTH                   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_WIDTH                 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_600_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_600_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_601_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_601_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_602_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_602_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_603_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_603_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH                10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_604_READ_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_604_WRITE_MASK                            0x1F0703FFU
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_WIDTH                 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_MASK           0x00070000U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_WIDTH                   3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_WIDTH                    5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2
+
+#define LPDDR4__DENALI_PHY_605_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_PHY_605_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_MASK       0x00000007U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_605
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_606_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_606_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_WIDTH                      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_WIDTH                     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_607_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_WIDTH                  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_SHIFT               24U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_608_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_608_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_WIDTH                16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2
+
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_WIDTH                 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2
+
+#define LPDDR4__DENALI_PHY_609_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_609_WRITE_MASK                            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOSET                0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_WIDTH                      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_WIDTH                     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_WIDTH                  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_610_READ_MASK                             0x1F010303U
+#define LPDDR4__DENALI_PHY_610_WRITE_MASK                            0x1F010303U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_WIDTH                           2U
+#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_WIDTH                          2U
+#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOSET                      0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_WDQLVL_IE_ON_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_WIDTH              5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_611_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_611_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_WIDTH         5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_MASK        0x00001F00U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH                5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_MASK          0x001F0000U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_WIDTH                  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_WIDTH                    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_612_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_612_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_613_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_613_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2
+
+#define LPDDR4__DENALI_PHY_614_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_614_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_615_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_615_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2
+
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2
+
+#define LPDDR4__DENALI_PHY_616_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_616_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2
+
+#define LPDDR4__DENALI_PHY_617_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_617_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2
+
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_618_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_618_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_618
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2
+
+#define LPDDR4__DENALI_PHY_619_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_619_WRITE_MASK                            0x00030703U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_620_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_620_WRITE_MASK                            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_620
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_620
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_621_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_621_WRITE_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT      24U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_622_READ_MASK                             0x001F7F7FU
+#define LPDDR4__DENALI_PHY_622_WRITE_MASK                            0x001F7F7FU
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_MASK      0x00007F00U
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT              8U
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_623_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_623
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_624_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_624_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_625_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_625_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_626_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_626_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_626
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_626
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_627_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_627_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_627
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_627
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_628_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_629_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_630_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_630_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_631_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_632_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_633_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_633_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_640_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_640_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2
+
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT      16U
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_641_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_641_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH            1U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR            0U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2
+
+#define LPDDR4__DENALI_PHY_642_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_642_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2
+
+#define LPDDR4__DENALI_PHY_643_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_643_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2
+
+#define LPDDR4__DENALI_PHY_644_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_644_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_644
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_645_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_645_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_646_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_647_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
+
+#define LPDDR4__DENALI_PHY_648_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_648_WRITE_MASK                            0x0003033FU
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_WIDTH                            2U
+#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_WIDTH                           2U
+#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2
+
+#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
new file mode 100644
index 0000000..29bdc46
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK                             0x07FF7F07U
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK                            0x07FF7F07U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_SHIFT          0U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_WIDTH        7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3
+
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK                             0x0703FF0FU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK                            0x0703FF0FU
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT      8U
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK                            0x010303FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT     0U
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK                            0x01030F3FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH                     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH                    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH                   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT     24U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH      1U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR      0U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK                            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT         8U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT      24U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK                            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT     8U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT     16U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK                            0x0101FF03U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH                      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH                      9U
+#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WIDTH           1U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOCLR           0U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOSET           0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__REG DENALI_PHY_777
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__FLD LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_778
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_779
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK                            0x7F0101FFU
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_WIDTH                           9U
+#define LPDDR4__PHY_DQ_IDLE_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_DQ_IDLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOSET                       0U
+#define LPDDR4__PHY_PDA_MODE_EN_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_PDA_MODE_EN_3__FLD LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_MASK        0x7F000000U
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_SHIFT               24U
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_WIDTH                7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_WIDTH                 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3
+
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH           1U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR           0U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT     24U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH      1U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR      0U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK                            0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_MASK            0x00007F00U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_WIDTH                    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT      16U
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK                            0x01FF000FU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_783
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3
+
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOSET                  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_783
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3
+
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_783
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK                            0x01FF0701U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_MASK                     0x00000001U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_SHIFT                             0U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOSET                             0U
+#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_784__PHY_LPDDR_3
+
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_MASK                 0x00000700U
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_WIDTH                         3U
+#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3
+
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_WIDTH                 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_785
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_WIDTH                32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_786
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK                            0x00000301U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOSET                    0U
+#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_787
+#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_WIDTH                     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_787
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_788
+#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_789
+#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_790
+#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_791
+#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_792
+#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_793
+#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK                            0x070F0107U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH           1U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR           0U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_WIDTH                 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK                            0x3F030001U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOSET                    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3
+
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOSET                 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_798
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_WIDTH                        2U
+#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_WIDTH                 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK                            0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_WIDTH                           8U
+#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_WIDTH                 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_WIDTH                 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_WIDTH                     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_WIDTH                   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3
+
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_MASK        0x03FFFF00U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_WIDTH               18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK                            0x00073FFFU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT       0U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
+
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_MASK          0x00003F00U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_WIDTH                  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3
+
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_WIDTH                       3U
+#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK                            0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT   0U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK      0x000F0000U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK    0x0F000000U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_WIDTH               8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3
+
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_SHIFT               16U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT       24U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH        1U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR        0U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_804
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_WIDTH                9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_805
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_806
+#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_807
+#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_808
+#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_809
+#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_WIDTH                       16U
+#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3
+
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOSET                    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3
+
+#define LPDDR4__DENALI_PHY_811_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_811_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_812_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_812_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT          0U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_812
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3
+
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT         16U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_812
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3
+
+#define LPDDR4__DENALI_PHY_813_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_813_WRITE_MASK                            0x00FF0001U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT          0U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH          1U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR          0U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3
+
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_WIDTH                   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_813
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3
+
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_WIDTH                      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3
+
+#define LPDDR4__DENALI_PHY_814_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_WIDTH                  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3
+
+#define LPDDR4__DENALI_PHY_815_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_815_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3
+
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3
+
+#define LPDDR4__DENALI_PHY_816_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_816_WRITE_MASK                            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_817_WRITE_MASK                            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT       24U
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_818_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT          8U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_WIDTH                      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3
+
+#define LPDDR4__DENALI_PHY_819_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_820_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_MASK          0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_WIDTH                 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_820
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_821_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_821_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_822_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_822_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_WIDTH                  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_822
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3
+
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_822
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_823_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_823_WRITE_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_823
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_824_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_WIDTH                 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_824
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_825_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_825_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_825
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_825
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_826_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_826_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT    0U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_826
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
+
+#define LPDDR4__DENALI_PHY_827_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_WIDTH                 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_827
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_828_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_828_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_828
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_828
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_829_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_WIDTH                32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_829
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_830_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_830
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3
+
+#define LPDDR4__DENALI_PHY_831_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_WIDTH                         31U
+#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_831
+#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3
+
+#define LPDDR4__DENALI_PHY_832_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_832_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_WIDTH                          6U
+#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_832
+#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3
+
+#define LPDDR4__DENALI_PHY_833_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_WIDTH                     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_833
+#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3
+
+#define LPDDR4__DENALI_PHY_834_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_834
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_835_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOSET                0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
+
+#define LPDDR4__DENALI_PHY_836_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
+
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
+
+#define LPDDR4__DENALI_PHY_837_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
+
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
+
+#define LPDDR4__DENALI_PHY_838_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
+
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
+
+#define LPDDR4__DENALI_PHY_839_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_839_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
+#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
+
+#define LPDDR4__DENALI_PHY_840_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH                        18U
+#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
+#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
+
+#define LPDDR4__DENALI_PHY_841_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
+
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH                       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
+
+#define LPDDR4__DENALI_PHY_842_READ_MASK                             0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_842_WRITE_MASK                            0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_WIDTH                   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3
+
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_SHIFT               16U
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_WIDTH                5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT          24U
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3
+
+#define LPDDR4__DENALI_PHY_843_READ_MASK                             0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_843_WRITE_MASK                            0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_MASK       0x000000FFU
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_MASK            0x00000300U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_WIDTH                    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_MASK      0x003F0000U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3
+
+#define LPDDR4__DENALI_PHY_844_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_844_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOSET                 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3
+
+#define LPDDR4__DENALI_PHY_845_READ_MASK                             0x01010703U
+#define LPDDR4__DENALI_PHY_845_WRITE_MASK                            0x01010703U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_MASK           0x00000003U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_WIDTH                   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_MASK             0x00000700U
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_WIDTH                     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH         1U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR         0U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_846_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_846_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT       0U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH       1U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR       0U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_847_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_847_WRITE_MASK                            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_WIDTH                    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_WIDTH                   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_WIDTH                   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_848_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_848_WRITE_MASK                            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_WIDTH                  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_WIDTH                  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_SHIFT         24U
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3
+
+#define LPDDR4__DENALI_PHY_849_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_849_WRITE_MASK                            0xFF01037FU
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_WIDTH                2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOSET                      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH                 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3
+
+#define LPDDR4__DENALI_PHY_850_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_850_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_WIDTH                    11U
+#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_850
+#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3
+
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_850
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3
+
+#define LPDDR4__DENALI_PHY_851_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_851_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_WIDTH                    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3
+
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_WIDTH                   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3
+
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT             24U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3
+
+#define LPDDR4__DENALI_PHY_852_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_852_WRITE_MASK                            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_WIDTH                       4U
+#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_WIDTH                        5U
+#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3
+
+#define LPDDR4__DENALI_PHY_853_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_853_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3
+
+#define LPDDR4__DENALI_PHY_854_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_854_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855_READ_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_855_WRITE_MASK                            0x007F1F1FU
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_WIDTH                    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_WIDTH                   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_WIDTH                 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3
+
+#define LPDDR4__DENALI_PHY_856_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_856_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_857_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_857_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_858_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_858_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_859_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_859_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH                10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_860_READ_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_860_WRITE_MASK                            0x1F0703FFU
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_WIDTH                 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_MASK           0x00070000U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_WIDTH                   3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_WIDTH                    5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3
+
+#define LPDDR4__DENALI_PHY_861_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_PHY_861_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_MASK       0x00000007U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_861
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_862_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_862_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_WIDTH                      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_WIDTH                     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_863_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_WIDTH                  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_SHIFT               24U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_864_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_864_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_WIDTH                16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3
+
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_WIDTH                 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3
+
+#define LPDDR4__DENALI_PHY_865_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_865_WRITE_MASK                            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOSET                0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_WIDTH                      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_WIDTH                     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_WIDTH                  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_866_READ_MASK                             0x1F010303U
+#define LPDDR4__DENALI_PHY_866_WRITE_MASK                            0x1F010303U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_WIDTH                           2U
+#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_WIDTH                          2U
+#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOSET                      0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_WDQLVL_IE_ON_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_SHIFT             24U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_WIDTH              5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_867_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_867_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_WIDTH         5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_MASK        0x00001F00U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH                5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_MASK          0x001F0000U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_WIDTH                  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_WIDTH                    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3
+
+#define LPDDR4__DENALI_PHY_868_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_868_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3
+
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3
+
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3
+
+#define LPDDR4__DENALI_PHY_869_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_869_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3
+
+#define LPDDR4__DENALI_PHY_870_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_870_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_871_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_871_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3
+
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3
+
+#define LPDDR4__DENALI_PHY_872_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_872_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3
+
+#define LPDDR4__DENALI_PHY_873_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_873_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3
+
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_874_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_874_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_874
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3
+
+#define LPDDR4__DENALI_PHY_875_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_875_WRITE_MASK                            0x00030703U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_876_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_876_WRITE_MASK                            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_876
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_876
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_877_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_877_WRITE_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT      24U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_878_READ_MASK                             0x001F7F7FU
+#define LPDDR4__DENALI_PHY_878_WRITE_MASK                            0x001F7F7FU
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_MASK      0x00007F00U
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT              8U
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_879_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_879
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3
+
+#define LPDDR4__DENALI_PHY_880_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_880_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3
+
+#define LPDDR4__DENALI_PHY_881_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_881_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_882_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_882_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_882
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_882
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_883_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_883_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_883
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_883
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_884_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_885_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_886_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_886_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_887_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_888_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_889_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_889_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_896_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_896_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3
+
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT      16U
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_897_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_897_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH            1U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR            0U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3
+
+#define LPDDR4__DENALI_PHY_898_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_898_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3
+
+#define LPDDR4__DENALI_PHY_899_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_899_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3
+
+#define LPDDR4__DENALI_PHY_900_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_900_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_900
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_901_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_901_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT            8U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_902_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT            8U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_903_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
+
+#define LPDDR4__DENALI_PHY_904_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_904_WRITE_MASK                            0x0003033FU
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_WIDTH                            2U
+#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_WIDTH                           2U
+#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3
+
+#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000..61ae622
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,6560 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK                               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK                              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET                                     0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH                                4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK                     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH                            16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK                               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK                              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH                               5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK                       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH                               4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH                                2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH                      8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH                  8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH                     8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT                16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH                 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH                   16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH                8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH                          8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH                   8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH                    8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH                  8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK                          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH                                 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH                                24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH                                24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH                               24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH                                24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH                               24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH                               24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH                               24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH                                24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH                               24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH                               24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH                               24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET                         0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK                              0x03030301U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK                             0x03030301U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET                         0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK                0x00030000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK                              0x01030101U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK                             0x01030101U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET                            0U
+#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20
+#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO
+
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET                              0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH                                2U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x01000000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET                     0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK                              0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK                             0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK                    0x0000003FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH                            6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK              0x00000100U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET                      0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK                              0x0303031FU
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK                             0x0303031FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH                              32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK                     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH                            32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH                                 16U
+#define LPDDR4__TDLL_F0__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0
+
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH                                 16U
+#define LPDDR4__TDLL_F1__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH                                 16U
+#define LPDDR4__TDLL_F2__REG DENALI_CTL_26
+#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2
+
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT      24U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH       2U
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET                              0U
+#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST
+
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK                  0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH                         24U
+#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG
+
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET                           0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK                              0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK                             0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK                   0x00007FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH                          15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH                        4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH                         32U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT                0U
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH               32U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK                              0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK                             0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH                      16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET                          0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH                                 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH                                 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH                                 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_38
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_38
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1
+
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_WIDTH                           4U
+#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS
+
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_MASK       0x01000000U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_SHIFT              24U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WIDTH               1U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOCLR               0U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOSET               0U
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_40
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_WIDTH                                 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_40
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_40__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_40
+#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_40
+#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_42
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_WIDTH                                 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_42
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_42__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_42
+#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_42
+#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_44
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_WIDTH                                 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_44
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_44__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_44
+#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_44
+#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_45
+#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_45
+#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_45
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_45
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK                              0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK                             0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_WIDTH                        3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_46
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_46__TCCD_MASK                             0x00001F00U
+#define LPDDR4__DENALI_CTL_46__TCCD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_46__TCCD_WIDTH                                     5U
+#define LPDDR4__TCCD__REG DENALI_CTL_46
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_46__TCCD
+
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_WIDTH                                5U
+#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_46
+#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_46__TCCD_L_F0
+
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_WIDTH                                  8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_46
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_46__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_WIDTH                                8U
+#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_47
+#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_47__TRRD_L_F0
+
+#define LPDDR4__DENALI_CTL_47__TRC_F0_MASK                           0x0001FF00U
+#define LPDDR4__DENALI_CTL_47__TRC_F0_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_47__TRC_F0_WIDTH                                   9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_47
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_47__TRC_F0
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_48
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_48__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_WIDTH                                  6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_48
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_WIDTH                                6U
+#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_48
+#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_L_F0
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_49__TRP_F0_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TRP_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_49__TRP_F0_WIDTH                                   8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_49
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_49__TRP_F0
+
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_WIDTH                                  9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_49
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_49__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_WIDTH                                5U
+#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_49
+#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_49__TCCD_L_F1
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_WIDTH                                  8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_50
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_WIDTH                                8U
+#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_50
+#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_L_F1
+
+#define LPDDR4__DENALI_CTL_50__TRC_F1_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_50__TRC_F1_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_50__TRC_F1_WIDTH                                   9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_50
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_50__TRC_F1
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_51
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_51__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_WIDTH                                  6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_51
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_WIDTH                                6U
+#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_51
+#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_L_F1
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_52__TRP_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_52__TRP_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_52__TRP_F1_WIDTH                                   8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_52
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_52__TRP_F1
+
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_WIDTH                                  9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_52
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_52__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_WIDTH                                5U
+#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_52
+#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_52__TCCD_L_F2
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_WIDTH                                  8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_53
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_WIDTH                                8U
+#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_53
+#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_L_F2
+
+#define LPDDR4__DENALI_CTL_53__TRC_F2_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_53__TRC_F2_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_53__TRC_F2_WIDTH                                   9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_53
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_53__TRC_F2
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_54
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_54__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_WIDTH                                  6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_54
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_WIDTH                                6U
+#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_54
+#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_L_F2
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_55__TRP_F2_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TRP_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_55__TRP_F2_WIDTH                                   8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_55
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_55__TRP_F2
+
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_WIDTH                                  9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_55
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_55__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_WIDTH                                  8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_55
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_55__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_56
+#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F0
+
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_WIDTH                                  8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_56
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_56__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_WIDTH                                  8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_56
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_56__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_57
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_57__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_WIDTH                                  5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_57
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_57__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_WIDTH                                8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_58
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_58__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_WIDTH                                6U
+#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_58
+#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_58__TCCDMW_F0
+
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_WIDTH                                  8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_58
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_58
+#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_AP_F1
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_WIDTH                                  8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_59
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_59__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_WIDTH                                  8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_59
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_59__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_60
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_60__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_WIDTH                                  5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_60
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_60__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_WIDTH                                8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_61
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_61__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_WIDTH                                6U
+#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_61
+#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_61__TCCDMW_F1
+
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_WIDTH                                  8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_61
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_61
+#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_AP_F2
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_WIDTH                                  8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_62
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_62__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_WIDTH                                  8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_62
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_62__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_63
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_63__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_WIDTH                                  5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_63
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_63__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK                              0x07073FFFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK                             0x07073FFFU
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_WIDTH                                8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_64
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_64__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_WIDTH                                6U
+#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_64
+#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_64__TCCDMW_F2
+
+#define LPDDR4__DENALI_CTL_64__TPPD_MASK                             0x00070000U
+#define LPDDR4__DENALI_CTL_64__TPPD_SHIFT                                    16U
+#define LPDDR4__DENALI_CTL_64__TPPD_WIDTH                                     3U
+#define LPDDR4__TPPD__REG DENALI_CTL_64
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_64__TPPD
+
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_WIDTH                             3U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_64
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_64__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK                              0xFFFF0107U
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK                             0xFFFF0107U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_WIDTH                             3U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_65
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_65__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOSET                              0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_65
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_65__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_WIDTH                                  8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_65
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_65__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_65__TWR_F0_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_65__TWR_F0_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_65__TWR_F0_WIDTH                                   8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_65
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_65__TWR_F0
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_WIDTH                                  8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_66
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_66__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_66__TWR_F1_MASK                           0x0000FF00U
+#define LPDDR4__DENALI_CTL_66__TWR_F1_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_66__TWR_F1_WIDTH                                   8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_66
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_66__TWR_F1
+
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_WIDTH                                  8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_66
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_66__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_66__TWR_F2_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_66__TWR_F2_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_66__TWR_F2_WIDTH                                   8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_66
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_66__TWR_F2
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_CTL_67__TMRR_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_67__TMRR_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_67__TMRR_WIDTH                                     4U
+#define LPDDR4__TMRR__REG DENALI_CTL_67
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_67__TMRR
+
+#define LPDDR4__DENALI_CTL_67__AP_MASK                               0x00000100U
+#define LPDDR4__DENALI_CTL_67__AP_SHIFT                                       8U
+#define LPDDR4__DENALI_CTL_67__AP_WIDTH                                       1U
+#define LPDDR4__DENALI_CTL_67__AP_WOCLR                                       0U
+#define LPDDR4__DENALI_CTL_67__AP_WOSET                                       0U
+#define LPDDR4__AP__REG DENALI_CTL_67
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_67__AP
+
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOSET                             0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_67
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_67__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOSET                             0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_67
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_WIDTH                                  8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_68__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_WIDTH                                  8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_68__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_WIDTH                                  8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_68__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_68__BSTLEN_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_68__BSTLEN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_68__BSTLEN_WIDTH                                   6U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_68
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_68__BSTLEN
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_70
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_70
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOSET                          0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_70
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_WIDTH                        2U
+#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_70
+#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOSET                         0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_71
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOSET                             0U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_71
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_71__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOSET                             0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_71
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_71__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_MASK           0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_WIDTH                  26U
+#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_72
+#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK                              0x01010001U
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOSET                          0U
+#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_73
+#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR
+
+#define LPDDR4__DENALI_CTL_73__AREFRESH_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WOSET                                 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_73
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_73__AREFRESH
+
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOSET                              0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_73
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_73__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOSET                              0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_73
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_73__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK                              0x03FF3F07U
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK                             0x03FF3F07U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_MASK               0x00000007U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_WIDTH                       3U
+#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_74
+#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x00003F00U
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          8U
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_74
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_WIDTH                                 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_74
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_74__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F0_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_75__TREF_F0_WIDTH                                 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_75
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_75__TREF_F0
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_WIDTH                                 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_76
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_76__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F1_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_77__TREF_F1_WIDTH                                 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_77
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_77__TREF_F1
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_WIDTH                                 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_78
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_78__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79__TREF_F2_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79__TREF_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_79__TREF_F2_WIDTH                                 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_79
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_79__TREF_F2
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_MASK                    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_WIDTH                           20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_80
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_80__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_81
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_82
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_83
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_84
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_85
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_85__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_86
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_86__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_86__PBR_EN_MASK                           0x01000000U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WOSET                                   0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_86
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_86__PBR_EN
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK                              0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK                             0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOSET                        0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_87
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_MASK                0x00FFFF00U
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_WIDTH                       16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_87
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_MASK            0x0F000000U
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_WIDTH                    4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_87
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK                              0x001F1F01U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK                             0x001F1F01U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOSET                          0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_88
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x00001F00U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_SHIFT               8U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_88
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x001F0000U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             16U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_88
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_WIDTH                                16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_89
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_89__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_WIDTH                                16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_89
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_89__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_WIDTH                                16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_90
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_90__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK                         0x00FF0000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH                                 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH                                 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK                              0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK                             0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_WIDTH                                 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_91
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_91__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_WIDTH                               5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK                              0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK                             0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_MASK                        0x0000000FU
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_WIDTH                                4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_92
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_WIDTH                               5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK                              0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK                             0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_MASK                        0x0000000FU
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_WIDTH                                4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_93
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_WIDTH                               5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK                              0x1F011F0FU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK                             0x1F011F0FU
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_MASK                        0x0000000FU
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_WIDTH                                4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_94
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_94__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_WIDTH                                5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH                                5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK                              0x00011F01U
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK                             0x00011F01U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_WIDTH                                5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_95
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_95__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_WIDTH                                 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_96__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH                                16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_WIDTH                                 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_97__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH                                16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_WIDTH                                 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_98__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH                                16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_WIDTH                                 16U
+#define LPDDR4__TXPR_F0__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_99__TXPR_F0
+
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH                                 16U
+#define LPDDR4__TXPR_F1__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_WIDTH                                16U
+#define LPDDR4__TXPR_F2__REG DENALI_CTL_100
+#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_100__TXPR_F2
+
+#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH                                  8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_100
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0
+
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK                       0x07000000U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH                               3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_101
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_101__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_MASK                     0x00001F00U
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK                     0x001F0000U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK                             0x1F07FF1FU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_WIDTH                              5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_102
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_102__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_102__TSR_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_102__TSR_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_102__TSR_F1_WIDTH                                  8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_102
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_102__TSR_F1
+
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK                       0x00070000U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH                               3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_MASK                     0x0000001FU
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_MASK                     0x00001F00U
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH                              5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK                             0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK                            0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_104__TSR_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_104__TSR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_104__TSR_F2_WIDTH                                  8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_104
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_104__TSR_F2
+
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_MASK                       0x00000700U
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_WIDTH                               3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_104
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_104__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK                     0x1F000000U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_MASK                     0x0000001FU
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_105__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_105__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH                              5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK                             0x01011F1FU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK                            0x01011F1FU
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_106
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_106
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET                     0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK        0x01000000U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT               24U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH                1U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR                0U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET                0U
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK                             0x7F000701U
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK                            0x7F000701U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_MASK           0x00000001U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOSET                   0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_107
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_MASK                       0x00000700U
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_WIDTH                               3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_107
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_107__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK                         0x001F0000U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH                                 5U
+#define LPDDR4__DFS_CMD__REG DENALI_CTL_107
+#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD
+
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK                      0x7F000000U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH                              7U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK                             0x00FFFF01U
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK                            0x00FFFF01U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOSET                               0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_108
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_108__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT                8U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK                             0xFF070707U
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK                            0xFF070707U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_WIDTH                           3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_110
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_MASK                    0x00000700U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_WIDTH                            3U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK                    0x00070000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH                            3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH                            8U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_WIDTH                            8U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_111
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_WIDTH                            8U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_111
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT     0U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT    16U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT    16U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT     0U
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_116
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET                         0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK                             0x00010103U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK                            0x00010103U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET                             0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK                             0x0000FF00U
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK                            0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH                             3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK          0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH                  8U
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH                   17U
+#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151
+#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK                             0x0F03FFFFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK                            0x0F03FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH                        18U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH                        4U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET                          0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH                             32U
+#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154
+#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH                             32U
+#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155
+#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_WIDTH                             32U
+#define LPDDR4__PPR_DATA_2__REG DENALI_CTL_156
+#define LPDDR4__PPR_DATA_2__FLD LPDDR4__DENALI_CTL_156__PPR_DATA_2
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_WIDTH                             32U
+#define LPDDR4__PPR_DATA_3__REG DENALI_CTL_157
+#define LPDDR4__PPR_DATA_3__FLD LPDDR4__DENALI_CTL_157__PPR_DATA_3
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK                             0xFFFF0103U
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK                            0xFFFF0103U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_MASK                      0x00000003U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_WIDTH                              2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_158
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_158__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_MASK               0x00000100U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOSET                       0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_158
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_WIDTH                                8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_158
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_158__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_WIDTH                                8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_158
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_158__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_WIDTH                                8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_159
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_159__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_WIDTH                                8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_159
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_159__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_WIDTH                                8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_159
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_159__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_WIDTH                                8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_159
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_159__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK                             0x0F0F0003U
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK                            0x0F0F0003U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_WIDTH                 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_160
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_160__LP_CMD_MASK                          0x00007F00U
+#define LPDDR4__DENALI_CTL_160__LP_CMD_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_160__LP_CMD_WIDTH                                  7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_160
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_160__LP_CMD
+
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_MASK          0x0F000000U
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_MASK           0x0000000FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT        8U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x0F000000U
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT               24U
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT      8U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT       16U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x0000000FU
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x00000F00U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT     16U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_MASK             0x0F000000U
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT       24U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_MASK                0x0000000FU
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x00000F00U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT                8U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT     24U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK                             0x00013F0FU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK                            0x00013F0FU
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_167
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_WIDTH                           6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_167
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOSET                         0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_167
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_MASK                 0x00000FFFU
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_WIDTH                        12U
+#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_168
+#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT
+
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_MASK              0x0FFF0000U
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_WIDTH                     12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_168
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK                             0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK                            0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_WIDTH                            3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_169
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_169__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_169__LP_STATE_MASK                        0x00007F00U
+#define LPDDR4__DENALI_CTL_169__LP_STATE_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_169__LP_STATE_WIDTH                                7U
+#define LPDDR4__LP_STATE__REG DENALI_CTL_169
+#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_169__LP_STATE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_WIDTH                        4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_WIDTH                         4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK                             0x000FFF07U
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK                            0x000FFF07U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_WIDTH                     3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_170
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_MASK                 0x000FFF00U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_WIDTH                        12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_170
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK                             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK                            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_WIDTH                  12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_WIDTH                    8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOSET                        0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOSET                      0U
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK                             0x0101FF01U
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOSET                            0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_176
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_MASK               0x0001FF00U
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_WIDTH                       9U
+#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_176
+#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY
+
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOSET                              0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_176
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_176__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK                             0x00000107U
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK                            0x00000107U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_WIDTH                             3U
+#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_177
+#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_177__DFS_DLL_OFF
+
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOSET                    0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_WIDTH                 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_178
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK                             0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK                            0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_WIDTH                  4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_WIDTH                 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_WIDTH                        2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_179
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK                             0x00000303U
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK                            0x00000303U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_MASK                       0x00000003U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_WIDTH                               2U
+#define LPDDR4__INIT_FREQ__REG DENALI_CTL_180
+#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_180__INIT_FREQ
+
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_WIDTH                        2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_180
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_181
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_182
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_183
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_184
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_185
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_186
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_187
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_188
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_189
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_MASK                   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_WIDTH                          27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_190
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_190__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_WIDTH                              8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_191
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_191__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_MASK                    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_WIDTH                           17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_191
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_191__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_WIDTH                  32U
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_192
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_WIDTH                   8U
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_193
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1
+
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_MASK              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_WIDTH                     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_193
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK                            0x0301FFFFU
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_MASK              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_WIDTH                     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_194
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOSET                    0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_194
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_WIDTH                      2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_194
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F0_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_196__TFC_F0_WIDTH                                 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_196
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_196__TFC_F0
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_197
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_199__TFC_F1_WIDTH                                 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_199
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_199__TFC_F1
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_200
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_201
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_201
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_202__TFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_202__TFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_202__TFC_F2_WIDTH                                 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_202
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_202__TFC_F2
+
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_202
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_202
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_203
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_203__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_204
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_204
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_205
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_205
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_206
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_206
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK                             0x01FFFF01U
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK                            0x01FFFF01U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOSET                             0U
+#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_207
+#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_207__MR4_DLL_RST
+
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_207
+#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_208
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_209
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_210
+#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_211
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_212
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_213
+#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_214
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_215
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_216
+#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_217
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_218
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_219
+#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_220
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_221
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_222
+#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_223
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_224
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_225
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_226
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_227
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_228
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_229
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_230
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_231
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_232
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_233
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_234
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_235
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_236
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_237
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_238
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_239
+#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_240
+#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_241
+#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_242
+#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_243
+#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_244
+#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_245
+#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_246
+#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_247
+#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_248
+#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_249
+#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_250
+#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_WIDTH                              8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_250
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_250__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_WIDTH                              8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_251
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_251__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_251
+#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_252
+#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_253
+#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_254
+#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_255
+#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_256
+#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_256
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_258
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_258
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_259
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_260
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_261
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_262
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_263
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_WIDTH                            17U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_264
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_264__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_WIDTH                            17U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_265
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_265__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_266
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_267
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_268
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_269
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_270
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_271
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_WIDTH                             8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_271
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_271__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_WIDTH                             8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_272
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_WIDTH                             8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_272
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_WIDTH                             8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_272
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_WIDTH                             8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_272
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_WIDTH                             8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_273
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_273__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_273
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_274
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_275
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_276
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_277
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_278
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_MASK                       0x0001FFFFU
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_WIDTH                              17U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_279
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_279__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_MASK            0x01000000U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_279
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_280
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_280
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOSET                   0U
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_280
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE
+
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_SHIFT                24U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOSET                 0U
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_280
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOSET                      0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_281
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOSET                    0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_281
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOSET                              0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_281
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_281__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_281
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_282
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_282
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_282
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_MASK                        0x03000000U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_WIDTH                                2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_282
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK                             0x3F030003U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK                            0x3F030003U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_MASK                        0x00000003U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_WIDTH                                2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_283
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_283__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_283__BIST_GO_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WOSET                                 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_283
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_283__BIST_GO
+
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_WIDTH                             2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_283
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_283__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_MASK                      0x3F000000U
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_WIDTH                              6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_283
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_283__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOSET                         0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_284
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOSET                         0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_284
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_WIDTH                   32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_285
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_MASK            0x00000007U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_WIDTH                    3U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_286
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_WIDTH                       32U
+#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_287
+#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_WIDTH                       32U
+#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_288
+#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_WIDTH                          3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_289
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_289__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_290
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_291
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_292
+#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_293
+#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK                             0x000FFF01U
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK                            0x000FFF01U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOSET                          0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_294
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_294__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_MASK                   0x000FFF00U
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_WIDTH                          12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_294
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_294__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_295_READ_MASK                             0x1F000FFFU
+#define LPDDR4__DENALI_CTL_295_WRITE_MASK                            0x1F000FFFU
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_WIDTH                         12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_295
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOSET                     0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_295
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_WIDTH                         5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_295
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_296_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_296_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_MASK             0x0000001FU
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_296
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_MASK             0x00001F00U
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_296
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_MASK                0x001F0000U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_WIDTH                        5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_296
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_WIDTH                         5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_296
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_WIDTH                  4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_297
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_WIDTH                      3U
+#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_297
+#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_301
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_305
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_305
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_306
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_306
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_307
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_307
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_308
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_308
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_309
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_309
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_MASK               0x000000FFU
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_WIDTH                       8U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_311
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_WIDTH                              12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_311
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_311__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_WIDTH                                12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_312
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_312__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_WIDTH                                12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_312
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_312__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK                             0x007F0FFFU
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK                            0x007F0FFFU
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_WIDTH                              12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_313
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_313__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_WIDTH                               7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_313
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_313__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_WIDTH                              12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_314__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_WIDTH                                12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_314__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_WIDTH                                12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_315
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_315__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_WIDTH                              12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_315
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_315__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK                            0x000FFF7FU
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_WIDTH                               7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_316
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_316__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_WIDTH                              12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_316
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_316__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_WIDTH                                12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_317
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_317__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_WIDTH                                12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_317
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_317__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK                             0x037F0FFFU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK                            0x037F0FFFU
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_WIDTH                              12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_318
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_318__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_WIDTH                               7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_318
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_318__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_MASK       0x03000000U
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_SHIFT              24U
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_WIDTH               2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_318
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK                             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK                            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_MASK                          0x0000000FU
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_WIDTH                                  4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_319
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOSET                          0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_319
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_WIDTH                             12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_319
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_319__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_WIDTH                             12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_320
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_WIDTH                             12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_320
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOSET                              0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_321
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_321__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOSET                             0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_321
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_321__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_321
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_321
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK                             0x03030303U
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK                            0x03030303U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_322
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_322
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_322
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_MASK                     0x03000000U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_322
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK                             0x0F0F0707U
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK                            0x0F0F0707U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_MASK                      0x00000007U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_323
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_MASK                      0x00000700U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_323
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_MASK                      0x000F0000U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_WIDTH                              4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_323
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_MASK                      0x0F000000U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_WIDTH                              4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_323
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_324
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_324
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK                             0x00FFFF03U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK                            0x00FFFF03U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_325
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_325__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_WIDTH                               16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_325
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_325__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_326
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_326
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK                             0x03FFFF03U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK                            0x03FFFF03U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_327
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_327__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_WIDTH                               16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_327
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_327__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_MASK                 0x03000000U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_WIDTH                         2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_327
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK                             0x1F011F01U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK                            0x1F011F01U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOSET                        0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_328
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_MASK                    0x00001F00U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_WIDTH                            5U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_328
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOSET                            0U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_328
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_328__APREBIT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_CTL_328__APREBIT_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_328__APREBIT_WIDTH                                 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_328
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_328__APREBIT
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_WIDTH                               8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_329
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_WIDTH                       8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_329
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOSET                             0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_329
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_329__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOSET                  0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_329
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOSET                           0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_330
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOSET                            0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_330
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_330__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOSET                             0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_330
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_330__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOSET                              0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_330
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_330__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOSET                         0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_331
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOSET                              0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_331
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_331__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOSET                            0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_331
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT        24U
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH         2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_331
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK                             0x0301011FU
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK                            0x0301011FU
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_MASK       0x0000001FU
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT               0U
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH               5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_332
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOSET                                 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_332
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_332__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOSET                   0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_332
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_WIDTH                        2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_332
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK                             0x07010F03U
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK                            0x07010F03U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_MASK                          0x00000003U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_WIDTH                                  2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_333
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_333__CS_MAP
+
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_WIDTH                        4U
+#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_333
+#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT
+
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOSET                        0U
+#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_333
+#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION
+
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_333
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK                             0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK                            0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_334
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_335
+#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK                             0x03011F0FU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK                            0x03011F0FU
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_336
+#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_WIDTH                              5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_336
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_336__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOSET                         0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_336
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_MASK                    0x03000000U
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_WIDTH                            2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_336
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_336__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK                            0x01010001U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOSET                         0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_337
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOSET                             0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_MASK         0x00010000U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_SHIFT                16U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOSET                 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOSET                  0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK                             0x01030303U
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK                            0x01030303U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_MASK             0x00000003U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_MASK             0x00000300U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_SHIFT                24U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOSET                 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_338
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK                             0x001F0101U
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK                            0x001F0101U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOSET                               0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_339
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_339__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOSET                               0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_339
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_339__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_WIDTH                               5U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_339
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_339__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_WIDTH                         20U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_340
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOSET                            0U
+#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_340
+#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_340__BG_ROTATE_EN
+
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOSET                           0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_341
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_WIDTH                      32U
+#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_WIDTH                        32U
+#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_343
+#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_343__INT_MASK_MASTER
+
+#define LPDDR4__DENALI_CTL_344_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_WIDTH                     32U
+#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_344
+#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_345_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_WIDTH                          16U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_345
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_WIDTH                    16U
+#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_345
+#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_346_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_WIDTH                          16U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_WIDTH                          16U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_347_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_WIDTH                    32U
+#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_347
+#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING
+
+#define LPDDR4__DENALI_CTL_348_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_WIDTH                      32U
+#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_348
+#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF
+
+#define LPDDR4__DENALI_CTL_349_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_WIDTH                        16U
+#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_349
+#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_MISC
+
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_WIDTH                         8U
+#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_349
+#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_BIST
+
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_WIDTH                           8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_349
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_350_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_WIDTH                          8U
+#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_DFI
+
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_WIDTH                           8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_350
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_WIDTH                         8U
+#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ
+
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_MASK                 0xFF000000U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_WIDTH                         8U
+#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_INIT
+
+#define LPDDR4__DENALI_CTL_351_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_WIDTH                         8U
+#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_351
+#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_MODE
+
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_WIDTH                       8U
+#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_351
+#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY
+
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_WIDTH                        32U
+#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_352
+#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_WIDTH                          16U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_353
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_WIDTH                       16U
+#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_353
+#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_WIDTH                          16U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_WIDTH                          16U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_WIDTH                       32U
+#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_355
+#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING
+
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_WIDTH                         32U
+#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_356
+#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_ACK_USERIF
+
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_MASK                    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_WIDTH                           16U
+#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_357
+#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_ACK_MISC
+
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_WIDTH                            8U
+#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_357
+#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_ACK_BIST
+
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_WIDTH                           8U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_357
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_WIDTH                             8U
+#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_ACK_DFI
+
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_WIDTH                           8U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_358
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_WIDTH                            8U
+#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_ACK_FREQ
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_WIDTH                            8U
+#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_ACK_INIT
+
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_WIDTH                            8U
+#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_359
+#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_ACK_MODE
+
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_WIDTH                          8U
+#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_359
+#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_ACK_PARITY
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_WIDTH                       32U
+#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_360
+#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_WIDTH                          16U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_361
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_361__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_MASK               0xFFFF0000U
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_WIDTH                      16U
+#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_361
+#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_WIDTH                          16U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_362
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_WIDTH                          16U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_362
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_WIDTH                      32U
+#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_363
+#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_WIDTH                        32U
+#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_364
+#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_364__INT_MASK_USERIF
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_WIDTH                          16U
+#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_365
+#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_365__INT_MASK_MISC
+
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_WIDTH                           8U
+#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_365
+#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_365__INT_MASK_BIST
+
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_WIDTH                           8U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_365
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_365__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_WIDTH                            8U
+#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_366__INT_MASK_DFI
+
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_WIDTH                           8U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_366
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_366__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_WIDTH                           8U
+#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_366__INT_MASK_FREQ
+
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_WIDTH                           8U
+#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_366__INT_MASK_INIT
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_WIDTH                           8U
+#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_367
+#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_367__INT_MASK_MODE
+
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_WIDTH                         8U
+#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_367
+#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_367__INT_MASK_PARITY
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_WIDTH                    32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_368
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK                             0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK                            0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_WIDTH                     3U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_MASK             0x000FFF00U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_WIDTH                    12U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_WIDTH                       7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_WIDTH                  6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_370
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_371
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_372
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_373
+#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_374
+#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_375
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_376
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_377
+#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_378
+#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_379
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_WIDTH                        3U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_380
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_WIDTH                  32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_381
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK                             0xFF033F07U
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK                            0xFF033F07U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_MASK           0x00000007U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_WIDTH                   3U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_MASK               0x00003F00U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_WIDTH                       6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_WIDTH                     2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_382
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK                             0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK                            0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_383
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_MASK                     0x00000F00U
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_383
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_383
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_383
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK                             0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK                            0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_384
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOSET                               0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOSET                               0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOSET                               0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_SHIFT                24U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOSET                 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_385
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK                             0x033F3F3FU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK                            0x033F3F3FU
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_MASK                  0x03000000U
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_386
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK                             0x3F030303U
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK                            0x3F030303U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_387
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_MASK                  0x00000300U
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_387
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_MASK                  0x00030000U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_387
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_387
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK                             0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK                            0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_388
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_388
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_388
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_388
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_389
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_390
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_391
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_392
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_MASK                  0x0000001FU
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_MASK                  0x001F0000U
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_393
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK                             0x0F070F07U
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK                            0x0F070F07U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK                             0x07010107U
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK                            0x07010107U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_395
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_MASK    0x00000100U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_SHIFT            8U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WIDTH            1U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOCLR            0U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOSET            0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_395
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT        16U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH         1U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR         0U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET         0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_395
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_395
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK                             0xFF010307U
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK                            0xFF010307U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_396
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_MASK                      0x00000300U
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_WIDTH                              2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_396
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_396__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOSET                           0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_396
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_396__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_396
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_397
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_400
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK                             0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK                            0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_MASK            0x007F0000U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_406
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_409
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_411
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK                             0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK                            0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_MASK            0x007F0000U
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_415
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_416
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_417
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_418
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_419
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_420
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_421
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2
+
+#define LPDDR4__DENALI_CTL_423_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_423_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_MASK            0x007F0000U
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2
+
+#define LPDDR4__DENALI_CTL_424_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_424_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_WIDTH                          16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_424
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_WIDTH                         8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_424
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_MASK             0x7F000000U
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_WIDTH                     7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_424
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_425_READ_MASK                             0x0FFFFF03U
+#define LPDDR4__DENALI_CTL_425_WRITE_MASK                            0x0FFFFF03U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_MASK                0x00000003U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_WIDTH                        2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_425
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_MASK                0x00FFFF00U
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_WIDTH                       16U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_425
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_WIDTH                   4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_425
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_426_READ_MASK                             0x01FF070FU
+#define LPDDR4__DENALI_CTL_426_WRITE_MASK                            0x01FF070FU
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_MASK            0x0000000FU
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_WIDTH                    4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_426
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_MASK                  0x00000700U
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_WIDTH                          3U
+#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_426
+#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_WIDTH                       8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_426
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_MASK     0x01000000U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_SHIFT            24U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WIDTH             1U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOCLR             0U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOSET             0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_426
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_427_READ_MASK                             0x07070701U
+#define LPDDR4__DENALI_CTL_427_WRITE_MASK                            0x07070701U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_MASK     0x00000001U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_SHIFT             0U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WIDTH             1U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOCLR             0U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOSET             0U
+#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__REG DENALI_CTL_427
+#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__FLD LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER
+
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_MASK            0x00000700U
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_MASK       0x00070000U
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_SHIFT              16U
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428_READ_MASK                             0x0F070707U
+#define LPDDR4__DENALI_CTL_428_WRITE_MASK                            0x0F070707U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_MASK            0x00000007U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_MASK       0x00000700U
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_SHIFT               8U
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_MASK                 0x00070000U
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_428
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_429_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_430_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_MASK              0x00000F00U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_431_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_432_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_MASK              0x00000F00U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433_READ_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_433_WRITE_MASK                            0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__NWR_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_433__NWR_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_433__NWR_F0_WIDTH                                  8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_433
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_433__NWR_F0
+
+#define LPDDR4__DENALI_CTL_434_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_434_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_434__NWR_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_434__NWR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_434__NWR_F1_WIDTH                                  8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_434
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_434__NWR_F1
+
+#define LPDDR4__DENALI_CTL_434__NWR_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_434__NWR_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_434__NWR_F2_WIDTH                                  8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_434
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_434__NWR_F2
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
new file mode 100644
index 0000000..a5966d8
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
@@ -0,0 +1,1986 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
+#define REG_LPDDR4_PHY_CORE_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1792_READ_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_1792_WRITE_MASK                           0x00000003U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_WIDTH                           2U
+#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1792
+#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1793_READ_MASK                            0x1F030101U
+#define LPDDR4__DENALI_PHY_1793_WRITE_MASK                           0x1F030101U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOSET                0U
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_SHIFT              8U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOSET              0U
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN
+
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_WIDTH                     2U
+#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX
+
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1793
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1794_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1795_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1796_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797_READ_MASK                            0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1797_WRITE_MASK                           0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1798_READ_MASK                            0x011F07FFU
+#define LPDDR4__DENALI_PHY_1798_WRITE_MASK                           0x011F07FFU
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH            11U
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1798
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY
+
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_WIDTH                5U
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1798
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT
+
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOSET                0U
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1798
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1799_READ_MASK                            0x07FF0100U
+#define LPDDR4__DENALI_PHY_1799_WRITE_MASK                           0x07FF0100U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_MASK           0x00000001U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOSET                   0U
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1799
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH        1U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR        0U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET        0U
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1799
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
+
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_MASK                0x07FF0000U
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_WIDTH                       11U
+#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1799
+#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START
+
+#define LPDDR4__DENALI_PHY_1800_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1800_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1800
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY
+
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOSET                   0U
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1800
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE
+
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOSET                0U
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1800
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT
+
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOSET                 0U
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1801
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR
+
+#define LPDDR4__DENALI_PHY_1802_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1802
+#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0
+
+#define LPDDR4__DENALI_PHY_1803_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1803
+#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1
+
+#define LPDDR4__DENALI_PHY_1804_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1804
+#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2
+
+#define LPDDR4__DENALI_PHY_1805_READ_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_PHY_1805_WRITE_MASK                           0x0101FF01U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_MASK               0x00000001U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOSET                       0U
+#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1805
+#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE
+
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH        9U
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1805
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET
+
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOSET                   0U
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1805
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1806_READ_MASK                            0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1806_WRITE_MASK                           0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_MASK               0x0000000FU
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_WIDTH                       4U
+#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1806
+#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_MASK                  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_WIDTH                         11U
+#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1806
+#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR
+
+#define LPDDR4__DENALI_PHY_1807_READ_MASK                            0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1807_WRITE_MASK                           0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK
+
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH           4U
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_MASK               0xFF000000U
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_WIDTH                       8U
+#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1808_READ_MASK                            0x01030007U
+#define LPDDR4__DENALI_PHY_1808_WRITE_MASK                           0x01030007U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT       0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH       3U
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
+
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS
+
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_MASK            0x00030000U
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_WIDTH                    2U
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1808
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE
+
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_MASK               0x01000000U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOSET                       0U
+#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR
+
+#define LPDDR4__DENALI_PHY_1809_READ_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1809_WRITE_MASK                           0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOSET                         0U
+#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1809
+#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE
+
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOSET                          0U
+#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1809
+#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS
+
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK     0x00FF0000U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH             8U
+#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1809
+#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT
+
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_WIDTH                 8U
+#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1809
+#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT
+
+#define LPDDR4__DENALI_PHY_1810_READ_MASK                            0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1810_WRITE_MASK                           0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_WIDTH                      2U
+#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET                0U
+#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_MASK        0x003F0000U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_WIDTH                6U
+#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH           8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT
+
+#define LPDDR4__DENALI_PHY_1811_READ_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_1811_WRITE_MASK                           0x010101FFU
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_MASK      0x000000FFU
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH              8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOSET               0U
+#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOSET                0U
+#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOSET                   0U
+#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START
+
+#define LPDDR4__DENALI_PHY_1812_READ_MASK                            0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1812_WRITE_MASK                           0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET           0U
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1812
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES
+
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET          0U
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1812
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_MASK             0x000F0000U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1812
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1812
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1813_READ_MASK                            0x0F010F0FU
+#define LPDDR4__DENALI_PHY_1813_WRITE_MASK                           0x0F010F0FU
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_MASK             0x0000000FU
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1813
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1813
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOSET                0U
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1813
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL
+
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1813
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1814_READ_MASK                            0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1814_WRITE_MASK                           0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK     0x00000F00U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK     0x000F0000U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET               0U
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1814
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL
+
+#define LPDDR4__DENALI_PHY_1815_READ_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1815_WRITE_MASK                           0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOSET             0U
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1815
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT    8U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET    0U
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1815
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_WIDTH                16U
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1815
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL
+
+#define LPDDR4__DENALI_PHY_1816_READ_MASK                            0x0001010FU
+#define LPDDR4__DENALI_PHY_1816_WRITE_MASK                           0x0001010FU
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK  0x0000000FU
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH          4U
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1816
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET          0U
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1816
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOSET                0U
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1816
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1817_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_WIDTH                    32U
+#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1817
+#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS
+
+#define LPDDR4__DENALI_PHY_1818_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_WIDTH                          16U
+#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1818
+#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT
+
+#define LPDDR4__DENALI_PHY_1819_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1819_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_MASK              0x00000001U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOSET                      0U
+#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1819
+#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1820_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1820_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3
+
+#define LPDDR4__DENALI_PHY_1821_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1821_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK   0x0F000000U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0
+
+#define LPDDR4__DENALI_PHY_1822_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1822_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK   0x0F000000U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1
+
+#define LPDDR4__DENALI_PHY_1823_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1823_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK   0x0F000000U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2
+
+#define LPDDR4__DENALI_PHY_1824_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1824_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK   0x0F000000U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH           4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3
+
+#define LPDDR4__DENALI_PHY_1825_READ_MASK                            0x00FF01FFU
+#define LPDDR4__DENALI_PHY_1825_WRITE_MASK                           0x00FF01FFU
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_WIDTH                    8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOSET                0U
+#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_WIDTH                  8U
+#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD
+
+#define LPDDR4__DENALI_PHY_1826_READ_MASK                            0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1826_WRITE_MASK                           0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_MASK          0x00001FFFU
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_WIDTH                 13U
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1826
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_WIDTH                 16U
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1826
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1827_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1827_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOSET               0U
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1827
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK
+
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_WIDTH                   8U
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1827
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL
+
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK    0x00030000U
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH            2U
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1827
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS
+
+#define LPDDR4__DENALI_PHY_1828_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1828
+#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1829_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1829
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1830_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1830_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1831_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1831
+#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1832_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1832
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1833_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1833_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1834_READ_MASK                            0x0F010101U
+#define LPDDR4__DENALI_PHY_1834_WRITE_MASK                           0x0F010101U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOSET                    0U
+#define LPDDR4__PHY_PLL_TESTOUT_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_PLL_TESTOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_MASK             0x00000100U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOSET                     0U
+#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT             16U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET              0U
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_MASK                0x0F000000U
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_WIDTH                        4U
+#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1834
+#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT
+
+#define LPDDR4__DENALI_PHY_1835_READ_MASK                            0x03FF01FFU
+#define LPDDR4__DENALI_PHY_1835_WRITE_MASK                           0x03FF01FFU
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_WIDTH                          8U
+#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP
+
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_MASK                 0x00000100U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOSET                         0U
+#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN
+
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_MASK        0x03FF0000U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH               10U
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG
+
+#define LPDDR4__DENALI_PHY_1836_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1836_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_WIDTH                      17U
+#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1836
+#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL
+
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOSET                   0U
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1836
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY
+
+#define LPDDR4__DENALI_PHY_1837_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1837
+#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM
+
+#define LPDDR4__DENALI_PHY_1838_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_MASK              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_WIDTH                     17U
+#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1838
+#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM
+
+#define LPDDR4__DENALI_PHY_1839_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_WIDTH                      17U
+#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1839
+#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM
+
+#define LPDDR4__DENALI_PHY_1840_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1840
+#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM
+
+#define LPDDR4__DENALI_PHY_1841_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1841
+#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM
+
+#define LPDDR4__DENALI_PHY_1842_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1842
+#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM
+
+#define LPDDR4__DENALI_PHY_1843_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1843
+#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM
+
+#define LPDDR4__DENALI_PHY_1844_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1844
+#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM
+
+#define LPDDR4__DENALI_PHY_1845_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_MASK                0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_WIDTH                       18U
+#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1845
+#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM
+
+#define LPDDR4__DENALI_PHY_1846_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1846
+#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM
+
+#define LPDDR4__DENALI_PHY_1847_READ_MASK                            0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1847_WRITE_MASK                           0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_MASK              0x000003FFU
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_WIDTH                     10U
+#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1847
+#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_MASK          0x1FFF0000U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_WIDTH                 13U
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1847
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1848_READ_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848_WRITE_MASK                           0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_MASK                 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_WIDTH                        13U
+#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1849_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_WIDTH              32U
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1849
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0
+
+#define LPDDR4__DENALI_PHY_1850_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1850_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1850
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK  0x00000700U
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1850
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1851_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_WIDTH                  24U
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1851
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1852_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1852
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0
+
+#define LPDDR4__DENALI_PHY_1853_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1853
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0
+
+#define LPDDR4__DENALI_PHY_1854_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1854
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0
+
+#define LPDDR4__DENALI_PHY_1855_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1855
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0
+
+#define LPDDR4__DENALI_PHY_1856_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1856_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1856
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0
+
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_MASK             0x7F000000U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_WIDTH                     7U
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1856
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0
+
+#define LPDDR4__DENALI_PHY_1857_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1857_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_WIDTH                 8U
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOSET                      0U
+#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0
+
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_MASK          0x00000001U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1858
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1859_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1859
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0
+
+#define LPDDR4__DENALI_PHY_1860_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1860_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_WIDTH                   8U
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1860
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0
+
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_MASK            0x0FFFFF00U
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_WIDTH                   20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1860
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1861_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK      0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH             20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1861
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0
+
+#define LPDDR4__DENALI_PHY_1862_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_MASK         0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_WIDTH                25U
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1862
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0
+
+#define LPDDR4__DENALI_PHY_1863_READ_MASK                            0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1863_WRITE_MASK                           0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_MASK           0x007FFFFFU
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_WIDTH                  23U
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1863
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0
+
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1863
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864_READ_MASK                            0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1864_WRITE_MASK                           0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865_READ_MASK                            0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1865_WRITE_MASK                           0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866_READ_MASK                            0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1866_WRITE_MASK                           0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1867_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_WIDTH                      16U
+#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1867
+#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL
+
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1867
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOSET                  0U
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1867
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR
+
+#define LPDDR4__DENALI_PHY_1868_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1868_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_WIDTH                 2U
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_WIDTH                     4U
+#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_MASK            0x01FF0000U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_WIDTH                    9U
+#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1869_READ_MASK                            0x00000F7FU
+#define LPDDR4__DENALI_PHY_1869_WRITE_MASK                           0x00000F7FU
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_WIDTH              7U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1869
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START
+
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_WIDTH               4U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1869
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK
+
+#define LPDDR4__DENALI_PHY_1870_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_WIDTH                32U
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1870
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1871_READ_MASK                            0x003F0101U
+#define LPDDR4__DENALI_PHY_1871_WRITE_MASK                           0x003F0101U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET             0U
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_MASK        0x003F0000U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_WIDTH                6U
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1872_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1872_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_MASK     0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH            16U
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1872
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_MASK         0x00010000U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1872
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOSET                0U
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1872
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1873_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1873_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT       0U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH       1U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR       0U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET       0U
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1873
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1874_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_WIDTH               32U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1874
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL
+
+#define LPDDR4__DENALI_PHY_1875_READ_MASK                            0x071F01FFU
+#define LPDDR4__DENALI_PHY_1875_WRITE_MASK                           0x071F01FFU
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH           8U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1875
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH
+
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_MASK             0x00000100U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOSET                     0U
+#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1875
+#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT
+
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_MASK           0x001F0000U
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_WIDTH                   5U
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1875
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP
+
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_MASK                0x07000000U
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_WIDTH                        3U
+#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1875
+#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE
+
+#define LPDDR4__DENALI_PHY_1876_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1876_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK  0x00000003U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK  0x00000300U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK  0x00030000U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK  0x03000000U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3
+
+#define LPDDR4__DENALI_PHY_1877_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_WIDTH                     32U
+#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1877
+#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE
+
+#define LPDDR4__DENALI_PHY_1878_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_MASK                0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_WIDTH                       26U
+#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1878
+#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE
+
+#define LPDDR4__DENALI_PHY_1879_READ_MASK                            0x00FF073FU
+#define LPDDR4__DENALI_PHY_1879_WRITE_MASK                           0x00FF073FU
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_MASK                0x0000003FU
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_WIDTH                        6U
+#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1879
+#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK
+
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_MASK         0x00000700U
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_WIDTH                 3U
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1879
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG
+
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH         8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1879
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC
+
+#define LPDDR4__DENALI_PHY_1880_READ_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1880_WRITE_MASK                           0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH           16U
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1880
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN
+
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_WIDTH                        3U
+#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1880
+#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN
+
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_WIDTH                         3U
+#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1880
+#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS
+
+#define LPDDR4__DENALI_PHY_1881_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1881
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1882_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1882
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1883_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1883
+#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1884_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1884
+#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1885_READ_MASK                            0x0F0FFF03U
+#define LPDDR4__DENALI_PHY_1885_WRITE_MASK                           0x0F0FFF03U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_MASK                 0x00000003U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_WIDTH                         2U
+#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1885
+#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN
+
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_MASK       0x000FFF00U
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_WIDTH              12U
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1885
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_WIDTH               4U
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1885
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1886_READ_MASK                            0x1F010101U
+#define LPDDR4__DENALI_PHY_1886_WRITE_MASK                           0x1F010101U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOSET                        0U
+#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1886
+#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK
+
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_MASK                     0x00000100U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_SHIFT                             8U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOSET                             0U
+#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1886
+#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1886__PHY_ERR_IE
+
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH     1U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR     0U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET     0U
+#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1886
+#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT        24U
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH         5U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1886
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1887_READ_MASK                            0x0707FF0FU
+#define LPDDR4__DENALI_PHY_1887_WRITE_MASK                           0x0707FF0FU
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_WIDTH               4U
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_MASK        0x0007FF00U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH               11U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS
+
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_MASK              0x07000000U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_WIDTH                      3U
+#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS
+
+#define LPDDR4__DENALI_PHY_1888_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_WIDTH                  18U
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1888
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1889_READ_MASK                            0x0703FFFFU
+#define LPDDR4__DENALI_PHY_1889_WRITE_MASK                           0x0703FFFFU
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_MASK             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_WIDTH                    18U
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1889
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG
+
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK    0x07000000U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH            3U
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1889
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1890_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1890_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOSET                         0U
+#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1890
+#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1891_READ_MASK                            0x00011FFFU
+#define LPDDR4__DENALI_PHY_1891_WRITE_MASK                           0x00011FFFU
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_MASK                   0x00001FFFU
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_WIDTH                          13U
+#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1891
+#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOSET                       0U
+#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1891
+#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1892_READ_MASK                            0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1892_WRITE_MASK                           0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_MASK           0x00000FFFU
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1892
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC
+
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_MASK          0x000F0000U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_WIDTH                  4U
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1892
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_WIDTH                     4U
+#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1892
+#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP
+
+#define LPDDR4__DENALI_PHY_1893_READ_MASK                            0x010103FFU
+#define LPDDR4__DENALI_PHY_1893_WRITE_MASK                           0x010103FFU
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_WIDTH                  10U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1893
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN
+
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOSET                0U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1893
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN
+
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET           0U
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1893
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE
+
+#define LPDDR4__DENALI_PHY_1894_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1894_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1894
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1894
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1895_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1895_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1895
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1895
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1896_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1896_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1896
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1896
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1897_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1897_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1897
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1897
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1898_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1898_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1898
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1898
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1899_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1899_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1899
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1899
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1900_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1900_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1900
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1901_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1901_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1901
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1902_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1902_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1902
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1903_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1903_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1903
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1904_READ_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_1904_WRITE_MASK                           0x00000007U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_MASK         0x00000007U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_WIDTH                 3U
+#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1904
+#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1905_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1905
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1906_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_MASK            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_WIDTH                   18U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1906
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1907_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_MASK             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_WIDTH                    31U
+#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1907
+#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE
+
+#define LPDDR4__DENALI_PHY_1908_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1908
+#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1909_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1909
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1910_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_MASK            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_WIDTH                   28U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1910
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1911_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1911
+#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1912_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912_WRITE_MASK                           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_MASK             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_WIDTH                    19U
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1912
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1913_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1913
+#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1914_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1914
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1915_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1915
+#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE
+
+#define LPDDR4__DENALI_PHY_1916_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1916
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1917_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1917
+#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE
+
+#define LPDDR4__DENALI_PHY_1918_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1918
+#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1919_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_MASK               0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_WIDTH                      30U
+#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1919
+#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1920_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_MASK              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_WIDTH                     28U
+#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1920
+#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1921_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1921
+#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE
+
+#define LPDDR4__DENALI_PHY_1922_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1922
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1923_READ_MASK                            0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1923_WRITE_MASK                           0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_MASK           0x00000007U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_WIDTH                   3U
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_MASK    0x00FFFF00U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH           16U
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0
+
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_WIDTH                 7U
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0
+
+#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
new file mode 100644
index 0000000..e36327f
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
@@ -0,0 +1,6892 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK                                0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK                               0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK                           0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH                                   1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET                                   0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT                              8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH                              4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH                              32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH                              32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK                                0x0101FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT                                      0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH                                     16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT                            16U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH                             1U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR                             0U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET                             0U
+#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3
+#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI
+
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT                         24U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET                          0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_4_READ_MASK                                0xFFFF0301U
+#define LPDDR4__DENALI_PI_4_WRITE_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET                             0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT                          8U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH                          2U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK                        0xFFFF0000U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT                               16U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH                               16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_5_READ_MASK                                0x030100FFU
+#define LPDDR4__DENALI_PI_5_WRITE_MASK                               0x030100FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH                               8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT                      8U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH                      1U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR                      0U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET                      0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT                            16U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH                             1U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR                             0U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET                             0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH                        2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_6_READ_MASK                                0x00000101U
+#define LPDDR4__DENALI_PI_6_WRITE_MASK                               0x00000101U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK          0x00000001U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH                  1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET                  0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK         0x00000100U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT                 8U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH                 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR                 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET                 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_7_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_8_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH                      20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_9_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH                       20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_11_READ_MASK                               0x0000011FU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK                              0x0000011FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH                         5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT                    8U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET                    0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_12_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT                               0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH                              32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK                               0x010F0101U
+#define LPDDR4__DENALI_PI_13_WRITE_MASK                              0x010F0101U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH                               1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET                               0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK                      0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT                              8U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH                              1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR                              0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET                              0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK                         0x000F0000U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT                                16U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH                                 4U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT                          24U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH                           1U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR                           0U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET                           0U
+#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13
+#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL
+
+#define LPDDR4__DENALI_PI_14_READ_MASK                               0x0F011F0FU
+#define LPDDR4__DENALI_PI_14_WRITE_MASK                              0x0F011F0FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK                        0x0000000FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH                                4U
+#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT                       8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH                       5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT                  16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH                   1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR                   0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET                   0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK                           0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT                                  24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH                                   4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK                               0x0101070FU
+#define LPDDR4__DENALI_PI_15_WRITE_MASK                              0x0101070FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK                          0x0000000FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT                                  0U
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH                                  4U
+#define LPDDR4__PI_TMPRR__REG DENALI_PI_15
+#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR
+
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK                        0x00000700U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT                                8U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH                                3U
+#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15
+#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT                   16U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET                    0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT                             24U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH                              1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR                              0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET                              0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK                               0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT                          0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH                         20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH                              1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR                              0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET                              0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK                               0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK                              0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH                         1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET                         0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT                             8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH                             1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR                             0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET                             0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT                         16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET                          0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH                        1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR                        0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK                               0x03010101U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK                              0x03010101U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK                0x00000100U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK                               0x03030303U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK                0x00000003U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK                               0x00000007U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK                              0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT                       0U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH                       3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT                            8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH                            1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR                            0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET                            0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT                            16U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH                             1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR                             0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET                             0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT                      24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_21_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT              8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH              1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR              0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_22_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT              8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH              1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR              0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT                      24U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH                       1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
+
+#define LPDDR4__DENALI_PI_23_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH                       1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT              8U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH              1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR              0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT                      16U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT                      24U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH                       1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
+
+#define LPDDR4__DENALI_PI_24_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH                       1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR                       0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT              8U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH              1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR              0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT                      16U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT                       24U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH                        1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR                        0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET                        0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_25_READ_MASK                               0x01000000U
+#define LPDDR4__DENALI_PI_25_WRITE_MASK                              0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK                   0x00000001U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH                           1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT                           8U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH                           1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT                    16U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH                     1U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR                     0U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET                     0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT                         24U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK                 0x00010000U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT                        16U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH                         1U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR                         0U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET                         0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT                    24U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET                     0U
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
+
+#define LPDDR4__DENALI_PI_27_READ_MASK                               0x3F030F00U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK                              0x3F030F00U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_SHIFT                              0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_MASK                    0x00000F00U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_SHIFT                            8U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_WIDTH                            4U
+#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK                       0x00030000U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT                              16U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH                               2U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK                        0x3F000000U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT                               24U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH                                6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_28_READ_MASK                               0x01FFFF3FU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK                              0x01FFFF3FU
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_MASK                          0x0000003FU
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_SHIFT                                  0U
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_WIDTH                                  6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_28
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_28__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK                 0x00FFFF00U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT                         8U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT                    24U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_29_READ_MASK                               0x0F010F01U
+#define LPDDR4__DENALI_PI_29_WRITE_MASK                              0x0F010F01U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT                      0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK                0x00000F00U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT                        8U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH                        4U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT                          16U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK                   0x0F000000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT                          24U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_30_READ_MASK                               0x00FF0101U
+#define LPDDR4__DENALI_PI_30_WRITE_MASK                              0x00FF0101U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_SHIFT                      0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOSET                      0U
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT                         16U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_31_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_32_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_33_READ_MASK                               0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33_WRITE_MASK                              0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK                       0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT                               8U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH                               4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK                       0x000F0000U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT                              16U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH                               4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT                             24U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH                              4U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_34_READ_MASK                               0x0000000FU
+#define LPDDR4__DENALI_PI_34_WRITE_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_MASK              0x0000000FU
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_SHIFT                      0U
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_WIDTH                      4U
+#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_34
+#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_PI_35_READ_MASK                               0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_MASK         0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_SHIFT                 0U
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_WIDTH                26U
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_35
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_PI_36_READ_MASK                               0x00000F07U
+#define LPDDR4__DENALI_PI_36_WRITE_MASK                              0x00000F07U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_MASK                      0x00000007U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_SHIFT                              0U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_WIDTH                              3U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_36
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_36__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_SHIFT                              8U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_WIDTH                              4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_36
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_36__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_SHIFT                             16U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_MASK                 0x01000000U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_SHIFT                        24U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WIDTH                         1U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOCLR                         0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOSET                         0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_37_READ_MASK                               0x0000030FU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK                              0x0000030FU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_MASK                    0x0000000FU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_SHIFT                            0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_WIDTH                            4U
+#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_MASK                       0x00000300U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SHIFT                               8U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_WIDTH                               2U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_38_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_39_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_40_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_41_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_SHIFT                            0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_42_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_SHIFT                            0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_43_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_SHIFT                            0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_44_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_SHIFT                            0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_45_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_SHIFT                            0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_46_READ_MASK                               0x0101010FU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_MASK                   0x0000000FU
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_SHIFT                           0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_WIDTH                           4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_SHIFT                     8U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_MASK              0x00010000U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_SHIFT                     16U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_MASK        0x01000000U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT               24U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH                1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR                0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET                0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_47_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_47_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_MASK         0x00000001U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_SHIFT                 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WIDTH                 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOCLR                 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOSET                 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_SHIFT                      8U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOSET                      0U
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_MASK         0x00010000U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT                16U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH                 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR                 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET                 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_SHIFT                          24U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_48_READ_MASK                               0x000F0F01U
+#define LPDDR4__DENALI_PI_48_WRITE_MASK                              0x000F0F01U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_SHIFT                      0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WIDTH                      1U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOCLR                      0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOSET                      0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_MASK                   0x00000F00U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_SHIFT                           8U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_MASK              0x000F0000U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_SHIFT                     16U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_WIDTH                      4U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_49_READ_MASK                               0x000003FFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_MASK                  0x000003FFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_SHIFT                          0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_WIDTH                         10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_50_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_50
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_51_READ_MASK                               0x0000FF0FU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK                              0x0000FF0FU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_MASK                0x0000000FU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_WIDTH                        4U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_51
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_52_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_52
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_53_READ_MASK                               0x00FFFF01U
+#define LPDDR4__DENALI_PI_53_WRITE_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_53
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_MASK                 0x00FFFF00U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_SHIFT                         8U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_53
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_54_READ_MASK                               0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_54_WRITE_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_SHIFT                    0U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_WIDTH                   16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_SHIFT                   16U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_WIDTH                    4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_MASK              0x0F000000U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_SHIFT                     24U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_WIDTH                      4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_55_READ_MASK                               0x01011F1FU
+#define LPDDR4__DENALI_PI_55_WRITE_MASK                              0x01011F1FU
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_55
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_MASK          0x00001F00U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_SHIFT                  8U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_WIDTH                  5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_55
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_SHIFT               16U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WIDTH                1U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOCLR                0U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOSET                0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_55
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WIDTH                        1U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOCLR                        0U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOSET                        0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_55
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_56_READ_MASK                               0x0F00FFFFU
+#define LPDDR4__DENALI_PI_56_WRITE_MASK                              0x0F00FFFFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_WIDTH                         8U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_SHIFT                         8U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_WIDTH                         8U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_SHIFT                             16U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOSET                              0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_56__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_MASK                    0x0F000000U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_SHIFT                           24U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_WIDTH                            4U
+#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW
+
+#define LPDDR4__DENALI_PI_57_READ_MASK                               0x030F0103U
+#define LPDDR4__DENALI_PI_57_WRITE_MASK                              0x030F0103U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_MASK                       0x00000003U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_SHIFT                               0U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_WIDTH                               2U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_57
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_57__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_MASK                      0x00000100U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_SHIFT                              8U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WIDTH                              1U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOCLR                              0U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOSET                              0U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_57
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_57__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_SHIFT                             16U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_WIDTH                              4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_57
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_57__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_MASK                   0x03000000U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_SHIFT                          24U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_WIDTH                           2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_57
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_58_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_58_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_SHIFT                         0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOSET                         0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_SHIFT                     8U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_MASK              0x00010000U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_SHIFT                     16U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_SHIFT                          24U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_59_READ_MASK                               0x0000FF0FU
+#define LPDDR4__DENALI_PI_59_WRITE_MASK                              0x0000FF0FU
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_MASK                   0x0000000FU
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_SHIFT                           0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_59
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_60_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_60
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_61_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_62_READ_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_62_WRITE_MASK                              0xFFFF0301U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOSET                        0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_WIDTH                     2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_SHIFT                        16U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_63_READ_MASK                               0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK                              0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_MASK                        0x0000001FU
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_SHIFT                                0U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_WIDTH                                5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_63
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_63__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_MASK                         0x00003F00U
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_WIDTH                                 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_63
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_63__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_SHIFT                               16U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_WIDTH                                5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_63
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_63__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_SHIFT                                24U
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_WIDTH                                 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_63
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_63__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_64_READ_MASK                               0xFF0F0F01U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK                              0xFF0F0F01U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_SHIFT                       0U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOSET                       0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_64
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK    0x00000F00U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT            8U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH            4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_64
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK     0x000F0000U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT            16U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH             4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_64
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_MASK            0xFF000000U
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_SHIFT                   24U
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_WIDTH                    8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_64
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_65_READ_MASK                               0x017F1FFFU
+#define LPDDR4__DENALI_PI_65_WRITE_MASK                              0x017F1FFFU
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_SHIFT                                0U
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_WIDTH                                8U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_65
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_65__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_SHIFT                       8U
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_65
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_SHIFT                      16U
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_WIDTH                       7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_65
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT       24U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH        1U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR        0U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET        0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_65
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_66_READ_MASK                               0xFF01FFFFU
+#define LPDDR4__DENALI_PI_66_WRITE_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_MASK        0x000000FFU
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_SHIFT                0U
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_WIDTH                8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_66
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT      8U
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH      8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_66
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK  0x00010000U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT         16U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH          1U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR          0U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET          0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_66
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_MASK         0xFF000000U
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_SHIFT                24U
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_WIDTH                 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_66
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_67_READ_MASK                               0x01010103U
+#define LPDDR4__DENALI_PI_67_WRITE_MASK                              0x01010103U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_MASK                        0x00000003U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_SHIFT                                0U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_WIDTH                                2U
+#define LPDDR4__PI_VREF_CS__REG DENALI_PI_67
+#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_67__PI_VREF_CS
+
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_SHIFT                            8U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WIDTH                            1U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOCLR                            0U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOSET                            0U
+#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_67
+#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN
+
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_SHIFT                   16U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WIDTH                    1U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOCLR                    0U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOSET                    0U
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_67
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK      0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT             24U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH              1U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR              0U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET              0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_67
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_68_READ_MASK                               0x0F0701FFU
+#define LPDDR4__DENALI_PI_68_WRITE_MASK                              0x0F0701FFU
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT        0U
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH        8U
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_68
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_SHIFT                         8U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOSET                         0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_MASK                 0x00070000U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_SHIFT                        16U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_WIDTH                         3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_MASK               0x0F000000U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_SHIFT                      24U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_WIDTH                       4U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_69_READ_MASK                               0x1F1F0F01U
+#define LPDDR4__DENALI_PI_69_WRITE_MASK                              0x1F1F0F01U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_MASK                  0x00000F00U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_SHIFT                          8U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_WIDTH                          4U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK   0x001F0000U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT          16U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH           5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK    0x1F000000U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT           24U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH            5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_70_READ_MASK                               0x030F0001U
+#define LPDDR4__DENALI_PI_70_WRITE_MASK                              0x030F0001U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_SHIFT                        0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WIDTH                        1U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOCLR                        0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOSET                        0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_SHIFT                             8U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOSET                             0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_MASK                   0x000F0000U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_SHIFT                          16U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_WIDTH                           4U
+#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_MASK                      0x03000000U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_WIDTH                              2U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_71_READ_MASK                               0x000000FFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_WIDTH                         8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_71
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_72_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_WIDTH                      32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_72
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_73_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_73
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_74_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_74_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_WIDTH                       16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_SHIFT                   16U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WIDTH                    1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOCLR                    0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOSET                    0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_SHIFT                    24U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_75_READ_MASK                               0x00030301U
+#define LPDDR4__DENALI_PI_75_WRITE_MASK                              0x00030301U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_MASK            0x00000300U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_SHIFT                    8U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_MASK       0x00030000U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT              16U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH               2U
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE
+
+#define LPDDR4__DENALI_PI_76_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK   0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT           0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH          32U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0
+
+#define LPDDR4__DENALI_PI_77_READ_MASK                               0x00010107U
+#define LPDDR4__DENALI_PI_77_WRITE_MASK                              0x00010107U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK   0x00000007U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT           0U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH           3U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_77
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1
+
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_SHIFT                     8U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_77
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN
+
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_SHIFT                          16U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WIDTH                           1U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOCLR                           0U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOSET                           0U
+#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_77
+#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM
+
+#define LPDDR4__DENALI_PI_78_READ_MASK                               0x010003FFU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK                              0x010003FFU
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_MASK                 0x000003FFU
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_SHIFT                         0U
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_WIDTH                        10U
+#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_78
+#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW
+
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_MASK      0x00010000U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT             16U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH              1U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR              0U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET              0U
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_78
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START
+
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_SHIFT                    24U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_78
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE
+
+#define LPDDR4__DENALI_PI_79_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_79_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_SHIFT                      8U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOSET                      0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_79
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_SHIFT                         16U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN
+
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_MASK          0x01000000U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT                 24U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH                  1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR                  0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOSET                  0U
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN
+
+#define LPDDR4__DENALI_PI_80_READ_MASK                               0x07030F01U
+#define LPDDR4__DENALI_PI_80_WRITE_MASK                              0x07030F01U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_SHIFT                     0U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOSET                     0U
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_80
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_MASK               0x00000F00U
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_SHIFT                       8U
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_WIDTH                       4U
+#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_80
+#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_MASK                      0x00030000U
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_SHIFT                             16U
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_WIDTH                              2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_80
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_80__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_MASK                       0x07000000U
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_SHIFT                              24U
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_WIDTH                               3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_80
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_80__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_81_READ_MASK                               0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK                              0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_81__PI_TCCD_MASK                           0x0000001FU
+#define LPDDR4__DENALI_PI_81__PI_TCCD_SHIFT                                   0U
+#define LPDDR4__DENALI_PI_81__PI_TCCD_WIDTH                                   5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_81
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_81__PI_TCCD
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_SHIFT                              8U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_WIDTH                              4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_81__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_SHIFT                             16U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_WIDTH                              4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_81__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_SHIFT                             24U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_WIDTH                              4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_81__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_82_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_SHIFT                             0U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_WIDTH                             4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_82__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_SHIFT                             8U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_WIDTH                             4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_82__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_SHIFT                            16U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_WIDTH                             4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_82__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_SHIFT                            24U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_WIDTH                             4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_82__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_83_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_SHIFT                             0U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_WIDTH                             4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_83__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_SHIFT                             8U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_WIDTH                             4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_83__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_SHIFT                            16U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_WIDTH                             4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_83__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_SHIFT                            24U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_WIDTH                             4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_83__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_84_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_84_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_SHIFT                             0U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_WIDTH                             4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_84__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_SHIFT                             8U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_WIDTH                             4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_84__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_SHIFT                            16U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_WIDTH                             4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_84__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_SHIFT                            24U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_WIDTH                             4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_84__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_85_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_SHIFT                             0U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_WIDTH                             4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_85__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_SHIFT                             8U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_WIDTH                             4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_85__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_SHIFT                            16U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_WIDTH                             4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_85__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_SHIFT                            24U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_WIDTH                             4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_85__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_86_READ_MASK                               0x0000000FU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_SHIFT                             0U
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_WIDTH                             4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_86
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_86__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_87_READ_MASK                               0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_MASK                     0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_SHIFT                             0U
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_WIDTH                            30U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_87
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_87__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_MASK                        0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_WIDTH                               29U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_88
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_88__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_89_READ_MASK                               0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_MASK                       0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_SHIFT                               0U
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_WIDTH                              30U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_89
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_89__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_90_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_92_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_92
+#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_PI_93_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_93
+#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_PI_94_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_95_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_95
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_96_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_PI_97_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_PI_98_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK                               0x011F3F07U
+#define LPDDR4__DENALI_PI_99_WRITE_MASK                              0x011F3F07U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_WIDTH                       3U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_MASK                         0x00003F00U
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_WIDTH                                 6U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_99
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_99__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_SHIFT                       16U
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_WIDTH                        5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_99
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_SHIFT                           24U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WIDTH                            1U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOCLR                            0U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOSET                            0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_99
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_100_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_WIDTH                         5U
+#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_100
+#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX
+
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_SHIFT                             8U
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_WIDTH                             5U
+#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_100
+#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_100__PI_ACT_N_MUX
+
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_SHIFT                             16U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_WIDTH                              5U
+#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_100
+#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_0
+
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_SHIFT                             24U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_WIDTH                              5U
+#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_100
+#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_1
+
+#define LPDDR4__DENALI_PI_101_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_SHIFT                             0U
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_WIDTH                             5U
+#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_RAS_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_SHIFT                             8U
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_WIDTH                             5U
+#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_CAS_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_MASK                      0x001F0000U
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_SHIFT                             16U
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_WIDTH                              5U
+#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_WE_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_MASK                    0x1F000000U
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_SHIFT                           24U
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_WIDTH                            5U
+#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_101
+#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_101__PI_BANK_MUX_0
+
+#define LPDDR4__DENALI_PI_102_READ_MASK                              0x0303011FU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK                             0x0303011FU
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_WIDTH                            5U
+#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_102
+#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_102__PI_BANK_MUX_1
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_SHIFT                     8U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOSET                     0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_MASK         0x00030000U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_SHIFT                16U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_WIDTH                 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_MASK         0x03000000U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_SHIFT                24U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_WIDTH                 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_103_READ_MASK                              0x00010303U
+#define LPDDR4__DENALI_PI_103_WRITE_MASK                             0x00010303U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_MASK         0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_SHIFT                 0U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_WIDTH                 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_103
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2
+
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_MASK         0x00000300U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_SHIFT                 8U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_WIDTH                 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_103
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3
+
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_MASK       0x00010000U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT              16U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH               1U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR               0U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET               0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_103
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_104_READ_MASK                              0x0703FFFFU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK                             0x0703FFFFU
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_MASK              0x0000FFFFU
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_SHIFT                      0U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_WIDTH                     16U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_104
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_MASK           0x00030000U
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_SHIFT                  16U
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_WIDTH                   2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_104
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_MASK                0x07000000U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_SHIFT                       24U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_WIDTH                        3U
+#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_104
+#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_PI_105_READ_MASK                              0xFF010301U
+#define LPDDR4__DENALI_PI_105_WRITE_MASK                             0xFF010301U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_SHIFT                               0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WIDTH                               1U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOCLR                               0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOSET                               0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_105__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_MASK                   0x00000300U
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_SHIFT                           8U
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_WIDTH                           2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_105__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_MASK        0x00010000U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_SHIFT               16U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WIDTH                1U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOCLR                0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOSET                0U
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE
+
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_MASK                    0xFF000000U
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_SHIFT                           24U
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_WIDTH                            8U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_105
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_105__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_106_READ_MASK                              0x00000101U
+#define LPDDR4__DENALI_PI_106_WRITE_MASK                             0x00000101U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_SHIFT                       0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WIDTH                       1U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOCLR                       0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOSET                       0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_MASK               0x00000100U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_SHIFT                       8U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WIDTH                       1U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOCLR                       0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOSET                       0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_107_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_WIDTH                 32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_108_READ_MASK                              0x0000FF07U
+#define LPDDR4__DENALI_PI_108_WRITE_MASK                             0x0000FF07U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_MASK          0x00000007U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_WIDTH                  3U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_MASK            0x0000FF00U
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_SHIFT                    8U
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_WIDTH                    8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_108
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_109_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_SHIFT                      0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_WIDTH                     32U
+#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_PI_110_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_WIDTH                     32U
+#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_PI_111_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_111_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_MASK                0x00000FFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_SHIFT                        0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_WIDTH                       12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_MASK                 0x0FFF0000U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_SHIFT                        16U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_WIDTH                        12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_112_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_113_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_113_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_114_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_115_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_115_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_116_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_117_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_117_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_118_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_119_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_119_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_120_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_121_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_121_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_122_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_123_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_124_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_125_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_126_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_127_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_128_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_129_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_130_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_131_READ_MASK                              0x0303070FU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK                             0x0303070FU
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_MASK                     0x00000700U
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_SHIFT                             8U
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_WIDTH                             3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_SHIFT                       16U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_WIDTH                        2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_MASK                 0x03000000U
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_SHIFT                        24U
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_WIDTH                         2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_132_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_133_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_133
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_134_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_134
+#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2
+
+#define LPDDR4__DENALI_PI_135_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_135
+#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3
+
+#define LPDDR4__DENALI_PI_136_READ_MASK                              0x0000007FU
+#define LPDDR4__DENALI_PI_136_WRITE_MASK                             0x0000007FU
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_MASK                  0x0000007FU
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_SHIFT                          0U
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_WIDTH                          7U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_136
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_137_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_SHIFT                          0U
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_137
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_138_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_138
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_139_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_139
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_140_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_SHIFT                          0U
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_140
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_141_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_SHIFT                          0U
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_141
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_142_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_SHIFT                          0U
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_142
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_143_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_SHIFT                          0U
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_143
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_144_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_SHIFT                          0U
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_144
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_145_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_145_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_SHIFT                              0U
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_WIDTH                              4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_145
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_145__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOSET                          0U
+#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_145
+#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN
+
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_SHIFT                             16U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WIDTH                              1U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOCLR                              0U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOSET                              0U
+#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_145
+#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_145__PI_CRC_CALC
+
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_SHIFT                      24U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOSET                       0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_145
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_146_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_PI_146_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_MASK        0x00000001U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT                0U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH                1U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR                0U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOSET                0U
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_MASK           0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_SHIFT                   8U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WIDTH                   1U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOCLR                   0U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOSET                   0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_MASK      0x00010000U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT             16U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH              1U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR              0U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOSET              0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_146
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_SHIFT                       24U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WIDTH                        1U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOCLR                        0U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOSET                        0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_146
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_147_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_SHIFT                        0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WIDTH                        1U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOCLR                        0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOSET                        0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_SHIFT                           8U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WIDTH                           1U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOCLR                           0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOSET                           0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_MASK         0x00010000U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_SHIFT                16U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WIDTH                 1U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOCLR                 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOSET                 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_SHIFT                     24U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOSET                      0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_148_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_SHIFT                            0U
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_WIDTH                           32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_148
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_148__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_149_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_WIDTH                         32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_149
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_150_READ_MASK                              0xFFFF0101U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_SHIFT                               0U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WIDTH                               1U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOCLR                               0U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOSET                               0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_150
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOSET                          0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_150
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_SHIFT                        16U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_WIDTH                        16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_150
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_151_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_MASK               0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_SHIFT                       0U
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_WIDTH                       8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_151
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_152_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_MASK                 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_SHIFT                         0U
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_WIDTH                        26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_152
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_153_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PI_153_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_MASK                    0x000000FFU
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_SHIFT                            0U
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_WIDTH                            8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_153__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_SHIFT                            8U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WIDTH                            1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOCLR                            0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOSET                            0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_153__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_154_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_154_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_SHIFT                          0U
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_WIDTH                         17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_154
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_154__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_155_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_155_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_WIDTH                24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_155
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOSET                            0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_155
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_156_READ_MASK                              0x0101000FU
+#define LPDDR4__DENALI_PI_156_WRITE_MASK                             0x0101000FU
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_MASK                    0x0000000FU
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_SHIFT                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_WIDTH                            4U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_156__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_MASK                    0x00000F00U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_SHIFT                            8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_WIDTH                            4U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_156__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_SHIFT                       16U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WIDTH                        1U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOCLR                        0U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOSET                        0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_156
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_SHIFT                           24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOSET                            0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_156__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_157_READ_MASK                              0xFF010F07U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK                             0xFF010F07U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_MASK                    0x00000007U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_SHIFT                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_WIDTH                            3U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_157__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WIDTH                     1U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOCLR                     0U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_158_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_158_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_SHIFT                     8U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WIDTH                     1U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOCLR                     0U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_SHIFT                    24U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_159_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_159_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WIDTH                     1U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOCLR                     0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_SHIFT                    16U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_SHIFT                    24U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WIDTH                     1U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOCLR                     0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_160_READ_MASK                              0xFF010FFFU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK                             0xFF010FFFU
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_SHIFT                             0U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_SHIFT                     8U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_SHIFT                    16U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WIDTH                     1U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOCLR                     0U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_SHIFT                            24U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_161_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_161_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_SHIFT                     0U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_SHIFT                     8U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WIDTH                     1U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOCLR                     0U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_SHIFT                            16U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_SHIFT                    24U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_162_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_SHIFT                     0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WIDTH                     1U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOCLR                     0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_SHIFT                             8U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_SHIFT                    16U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_SHIFT                    24U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WIDTH                     1U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOCLR                     0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_163_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_163_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_SHIFT                             0U
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_163
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_163__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_SHIFT                        0U
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_WIDTH                        8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_164
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_165_READ_MASK                              0x011F1F01U
+#define LPDDR4__DENALI_PI_165_WRITE_MASK                             0x011F1F01U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_SHIFT                              0U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WIDTH                              1U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOCLR                              0U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOSET                              0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_165
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_165__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_MASK            0x00001F00U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_SHIFT                    8U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_WIDTH                    5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_165
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_MASK            0x001F0000U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_SHIFT                   16U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_WIDTH                    5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_165
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_SHIFT                           24U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WIDTH                            1U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOCLR                            0U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOSET                            0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_165
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_165__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_166_READ_MASK                              0x01010103U
+#define LPDDR4__DENALI_PI_166_WRITE_MASK                             0x01010103U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_MASK                  0x00000003U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_WIDTH                          2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_166
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_SHIFT                            8U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WIDTH                            1U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOCLR                            0U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOSET                            0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_166
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_166__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WIDTH                        1U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOCLR                        0U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOSET                        0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_166
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_SHIFT                           24U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WIDTH                            1U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOCLR                            0U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOSET                            0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_166
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_166__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_167_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_167_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_SHIFT                            0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WIDTH                            1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOCLR                            0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOSET                            0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_167__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_SHIFT                            8U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WIDTH                            1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOCLR                            0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOSET                            0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_167__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_SHIFT                           16U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WIDTH                            1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOCLR                            0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOSET                            0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_167__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_SHIFT                           24U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WIDTH                            1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOCLR                            0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOSET                            0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_167__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_168_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_168_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_SHIFT                            0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WIDTH                            1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOCLR                            0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOSET                            0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_168__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_SHIFT                            8U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WIDTH                            1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOCLR                            0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOSET                            0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_168__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_SHIFT                           16U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WIDTH                            1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOCLR                            0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOSET                            0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_168__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_SHIFT                           24U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WIDTH                            1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOCLR                            0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOSET                            0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_168__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_169_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_169_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_SHIFT                            0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WIDTH                            1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOCLR                            0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOSET                            0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_169__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_SHIFT                            8U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WIDTH                            1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOCLR                            0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOSET                            0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_169__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_SHIFT                           16U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WIDTH                            1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOCLR                            0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOSET                            0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_169__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_SHIFT                           24U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WIDTH                            1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOCLR                            0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOSET                            0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_169__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_170_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_170_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_SHIFT                            0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WIDTH                            1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOCLR                            0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOSET                            0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_170__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_SHIFT                            8U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WIDTH                            1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOCLR                            0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOSET                            0U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_170__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_SHIFT                           16U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WIDTH                            1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOCLR                            0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOSET                            0U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_170__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_SHIFT                           24U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WIDTH                            1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOCLR                            0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOSET                            0U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_170__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_171_READ_MASK                              0x00FF0101U
+#define LPDDR4__DENALI_PI_171_WRITE_MASK                             0x00FF0101U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_SHIFT                            0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WIDTH                            1U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOCLR                            0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOSET                            0U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_171
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_171__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_SHIFT                            8U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WIDTH                            1U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOCLR                            0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOSET                            0U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_171
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_171__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_SHIFT                16U
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_WIDTH                 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_171
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_172_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_MASK                    0x000001FFU
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_SHIFT                            0U
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_WIDTH                            9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_172
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_172__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_173_READ_MASK                              0x0000001FU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_MASK          0x0000001FU
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_SHIFT                  0U
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_WIDTH                  5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_173
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_174_READ_MASK                              0x0F011F01U
+#define LPDDR4__DENALI_PI_174_WRITE_MASK                             0x0F011F01U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_MASK           0x00000001U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_SHIFT                   0U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WIDTH                   1U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOCLR                   0U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOSET                   0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_174
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_MASK                    0x00001F00U
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_SHIFT                            8U
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_WIDTH                            5U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_174
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_174__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_SHIFT                    16U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOSET                     0U
+#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_174
+#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN
+
+#define LPDDR4__DENALI_PI_174__PI_CATR_MASK                          0x0F000000U
+#define LPDDR4__DENALI_PI_174__PI_CATR_SHIFT                                 24U
+#define LPDDR4__DENALI_PI_174__PI_CATR_WIDTH                                  4U
+#define LPDDR4__PI_CATR__REG DENALI_PI_174
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_174__PI_CATR
+
+#define LPDDR4__DENALI_PI_175_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_175_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_SHIFT                          0U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOSET                          0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_175
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_175__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_SHIFT                    8U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WIDTH                    1U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOCLR                    0U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOSET                    0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_175
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_MASK                 0x00010000U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_SHIFT                        16U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOSET                         0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_175
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_MASK           0x01000000U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_SHIFT                  24U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WIDTH                   1U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOCLR                   0U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOSET                   0U
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_175
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ
+
+#define LPDDR4__DENALI_PI_176_READ_MASK                              0xFFFF0701U
+#define LPDDR4__DENALI_PI_176_WRITE_MASK                             0xFFFF0701U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_MASK         0x00000001U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_SHIFT                 0U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WIDTH                 1U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOCLR                 0U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOSET                 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_176
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK    0x00000700U
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT            8U
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH            3U
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_176
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY
+
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_MASK                      0xFFFF0000U
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_SHIFT                             16U
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TVREF_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F1
+
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_MASK                      0xFFFF0000U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_SHIFT                             16U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_177
+#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F2
+
+#define LPDDR4__DENALI_PI_178_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_SHIFT                               8U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_179_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT             0U
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_179
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_180_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT             0U
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_180
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_181_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_181_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT             0U
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_181
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_MASK                     0x000FFF00U
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_181
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_181__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_182_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_182_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_MASK                     0x00000FFFU
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_182
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_182
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_183_READ_MASK                              0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_183_WRITE_MASK                             0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_MASK                      0x0000007FU
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_183__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_MASK               0x00003F00U
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_SHIFT                     16U
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK  0xFF000000U
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT         24U
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0
+
+#define LPDDR4__DENALI_PI_184_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_184_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_MASK                 0x0000007FU
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_184
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_MASK                      0x00007F00U
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_SHIFT                              8U
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_184__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_MASK               0x003F0000U
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_SHIFT                     24U
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_PI_185_READ_MASK                              0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_185_WRITE_MASK                             0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK  0x000000FFU
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT          0U
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_185
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1
+
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_MASK                 0x00007F00U
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_185
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_MASK                      0x007F0000U
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_SHIFT                             16U
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_185
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_185__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_MASK               0x3F000000U
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_SHIFT                      24U
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_185
+#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_PI_186_READ_MASK                              0x007FFF0FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK                             0x007FFF0FU
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_SHIFT                      0U
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_186
+#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT          8U
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_186
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2
+
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_MASK                 0x007F0000U
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_186
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_187_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_187
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_187__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_188_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_WIDTH                              20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_188__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_189_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_189__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_190_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_WIDTH                              20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_190
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_190__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_191_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_191_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_191
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_191__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_192_READ_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_192_WRITE_MASK                             0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_WIDTH                              20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_192
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_192__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_192
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_193_READ_MASK                              0x03030F0FU
+#define LPDDR4__DENALI_PI_193_WRITE_MASK                             0x03030F0FU
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_193
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_SHIFT                    8U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_193
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_193
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_MASK                   0x03000000U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_193
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_194_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_194_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_194
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_MASK              0x0003FF00U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_SHIFT                      8U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_195_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_MASK              0x03FF0000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_SHIFT                     16U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_196_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WIDTH                             1U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOCLR                             0U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_196
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_MASK                     0x01000000U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WIDTH                             1U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOCLR                             0U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_196
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_197_READ_MASK                              0x0F0F01FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK                             0x0F0F01FFU
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WIDTH                             1U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOCLR                             0U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_197
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_197__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_197
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_197__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_197
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_198_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_198
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_MASK                 0x00000F00U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_198
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_198
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_199_WRITE_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_MASK                 0x0000003FU
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_MASK                 0x00003F00U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_MASK                 0x003F0000U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_MASK                 0x3F000000U
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_199
+#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_200_READ_MASK                              0x03033F3FU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK                             0x03033F3FU
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_MASK                 0x0000003FU
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_200
+#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_MASK                 0x00003F00U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_200
+#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_200
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_SHIFT                     24U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_200
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_201_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_201_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_MASK              0x00000300U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_SHIFT                      8U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_SHIFT                     24U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_202_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_MASK                    0x000000FFU
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_SHIFT                            8U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_SHIFT                           16U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2
+
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_SHIFT                     24U
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_202
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_203_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_203_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_SHIFT                     24U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_204_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_204_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_SHIFT                       8U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_SHIFT                    16U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_SHIFT                     24U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_205_READ_MASK                              0xFF030303U
+#define LPDDR4__DENALI_PI_205_WRITE_MASK                             0xFF030303U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_SHIFT                       8U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_SHIFT                    16U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_SHIFT                         24U
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_205
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_206_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_SHIFT                          0U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_206
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_SHIFT                          8U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_206
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_206
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_206
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_207_READ_MASK                              0x070707FFU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK                             0x070707FFU
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_207
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_MASK            0x00000700U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_SHIFT                    8U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_MASK            0x00070000U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_MASK            0x07000000U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_SHIFT                   24U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_208_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_SHIFT                      0U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_SHIFT                16U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_209_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_SHIFT                16U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_210_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_SHIFT                      0U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_SHIFT                16U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_211_READ_MASK                              0x1F030303U
+#define LPDDR4__DENALI_PI_211_WRITE_MASK                             0x1F030303U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_MASK                   0x00000300U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_211
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_211__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_212_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_212
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_212__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_212
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_212__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_213_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_213__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_213
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_213__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_214_READ_MASK                              0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK                             0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_214
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_214__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_215_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_215_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_215
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_215
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_216_READ_MASK                              0x03FF1F1FU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK                             0x03FF1F1FU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_MASK                0x0000001FU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_MASK                 0x00001F00U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_217_READ_MASK                              0x1F1F03FFU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_217
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_218_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_218
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_218
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_219_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT     0U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT      8U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT    16U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     24U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_220_READ_MASK                              0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT     0U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT      8U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_SHIFT                  16U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_MASK           0x0F000000U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_SHIFT                  24U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_221_READ_MASK                              0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_221_WRITE_MASK                             0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_MASK           0x0000000FU
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_221
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_SHIFT                  8U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_WIDTH                                5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_221__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_222_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_222
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_222__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_SHIFT                  8U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_SHIFT                               16U
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_WIDTH                                5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_222__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_223_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_223__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_SHIFT                  8U
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_SHIFT                               16U
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_WIDTH                                5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_223__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_224_READ_MASK                              0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK                             0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_224
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_224__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_MASK            0xFFFFFF00U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_SHIFT                    8U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_224
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_225_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_225
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_226_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_MASK            0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_226
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_227_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_SHIFT                 0U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_227
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_228_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_MASK            0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_SHIFT                 0U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_229
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_229
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_230_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_WIDTH                               10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_230
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_230__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_230
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_231_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_231_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_SHIFT                                0U
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_WIDTH                               10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_231
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_231__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_231
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_232_READ_MASK                              0x030303FFU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK                             0x030303FFU
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_SHIFT                                0U
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_WIDTH                               10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_232
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_232__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_MASK                    0x00030000U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_SHIFT                           16U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_232
+#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F0
+
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_MASK                    0x03000000U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_SHIFT                           24U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_232
+#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F1
+
+#define LPDDR4__DENALI_PI_233_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_233_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_MASK                    0x00000003U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_233
+#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_233__PI_VREF_EN_F2
+
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_233
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_234_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT   16U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_234
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT    24U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_234
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_235_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_SHIFT                  0U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_SHIFT                          8U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_235
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_SHIFT                         24U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0
+
+#define LPDDR4__DENALI_PI_236_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_236
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT                   8U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_236
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_SHIFT                    16U
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT   16U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_237
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT    24U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_237
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_238_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_SHIFT                  0U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_SHIFT                          8U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_238
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1
+
+#define LPDDR4__DENALI_PI_239_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_239
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT                   8U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_239
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_SHIFT                    16U
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_239
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_240_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_240
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT   16U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_240
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT    24U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_240
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_241_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_SHIFT                  0U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_SHIFT                          8U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_SHIFT                      16U
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_241
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_SHIFT                         24U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2
+
+#define LPDDR4__DENALI_PI_242_READ_MASK                              0x0303FFFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_242
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT                   8U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_242
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_MASK            0x00030000U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_SHIFT                   16U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_242
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0
+
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_MASK            0x03000000U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_SHIFT                   24U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_242
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1
+
+#define LPDDR4__DENALI_PI_243_READ_MASK                              0xFFFFFF03U
+#define LPDDR4__DENALI_PI_243_WRITE_MASK                             0xFFFFFF03U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_243
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2
+
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_WIDTH                                8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_243__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_244_READ_MASK                              0x00FF3F1FU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK                             0x00FF3F1FU
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_244__PI_TCCD_L_F0
+
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_MASK                       0x00003F00U
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_WIDTH                                8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_245_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_245
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_246_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_246__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_247_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_WIDTH                                8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_247__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMOD_F0
+
+#define LPDDR4__DENALI_PI_248_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0
+
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0
+
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_248
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_SHIFT                               24U
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_WIDTH                                8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_248
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_249_READ_MASK                              0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK                             0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_249__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_SHIFT                             8U
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_249__PI_TCCD_L_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_MASK                       0x003F0000U
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_SHIFT                               24U
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_WIDTH                                8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_250_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_250
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_251_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_251__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_252_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_WIDTH                                8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_252__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_SHIFT                               8U
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_SHIFT                              24U
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMOD_F1
+
+#define LPDDR4__DENALI_PI_253_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1
+
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1
+
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_253
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_SHIFT                               24U
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_WIDTH                                8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_253
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_254_READ_MASK                              0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK                             0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_254__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_254__PI_TCCD_L_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_MASK                       0x003F0000U
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_SHIFT                               24U
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_WIDTH                                8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_255_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_255
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_256_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_SHIFT                            24U
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_256__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_WIDTH                                8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_257__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_SHIFT                               8U
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_SHIFT                              24U
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMOD_F2
+
+#define LPDDR4__DENALI_PI_258_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2
+
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2
+
+#define LPDDR4__DENALI_PI_259_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_259
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT              0U
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_260
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_261
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_262_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT              0U
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_262
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_263_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_263
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_264_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT              0U
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_264
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_265_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_265
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_MASK                       0xFFFF0000U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_265
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_266_READ_MASK                              0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK                             0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_266
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_266__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_MASK                     0x003F0000U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_266
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_266
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_267_READ_MASK                              0x00FFFF3FU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK                             0x00FFFF3FU
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_MASK                     0x0000003FU
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_267
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_267__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_MASK                       0x00FFFF00U
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_267
+#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_267__PI_TDLL_F0
+
+#define LPDDR4__DENALI_PI_268_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_268
+#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F1
+
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_MASK                       0xFFFF0000U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_268
+#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F2
+
+#define LPDDR4__DENALI_PI_269_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F0
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F0
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F1
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F1
+
+#define LPDDR4__DENALI_PI_270_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRX_F2
+
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRE_F2
+
+#define LPDDR4__DENALI_PI_271_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_271
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_271__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_272_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_272
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_272__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_273_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_273
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_273__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_274_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_274
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_274__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_275_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_275
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_275__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_276_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_276
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_276__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_277_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_277
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_277__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_278_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_278
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_278__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_279_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_279
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_279__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_280_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_280
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_280__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_281_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_281
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_281__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_282_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_282
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_282__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_283_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_283
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_283__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_284_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_284
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_284__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_285_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_285_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_285
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_285__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_SHIFT                           16U
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_WIDTH                           12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_285
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_285__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_286_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_SHIFT                            0U
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_WIDTH                           12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_286
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_286__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_286
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_286__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_287_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_287
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_287__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_SHIFT                            8U
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_WIDTH                           12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_287
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_287__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_288_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_SHIFT                            0U
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_WIDTH                           12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_288
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_288__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_288
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_288__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_289_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_289
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_289__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_SHIFT                            8U
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_WIDTH                           12U
+#define LPDDR4__PI_RESERVED58__REG DENALI_PI_289
+#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_289__PI_RESERVED58
+
+#define LPDDR4__DENALI_PI_290_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_SHIFT                            0U
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_WIDTH                           12U
+#define LPDDR4__PI_RESERVED59__REG DENALI_PI_290
+#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_290__PI_RESERVED59
+
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_290
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_290__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_291_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_291
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_291__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_SHIFT                            8U
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_WIDTH                           12U
+#define LPDDR4__PI_RESERVED60__REG DENALI_PI_291
+#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_291__PI_RESERVED60
+
+#define LPDDR4__DENALI_PI_292_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_SHIFT                            0U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_WIDTH                           12U
+#define LPDDR4__PI_RESERVED61__REG DENALI_PI_292
+#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_292__PI_RESERVED61
+
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_SHIFT                           16U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_WIDTH                           12U
+#define LPDDR4__PI_RESERVED62__REG DENALI_PI_292
+#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_292__PI_RESERVED62
+
+#define LPDDR4__DENALI_PI_293_READ_MASK                              0x030F0F0FU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK                             0x030F0F0FU
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT                0U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_MASK        0x00000F00U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT                8U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_MASK        0x000F0000U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT               16U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_MASK           0x03000000U
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_SHIFT                  24U
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_293
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_PI_294_READ_MASK                              0x07070303U
+#define LPDDR4__DENALI_PI_294_WRITE_MASK                             0x07070303U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_MASK           0x00000003U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_294
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_MASK           0x00000300U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_SHIFT                   8U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_294
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_294
+#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_MASK               0x07000000U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_294
+#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_PI_295_READ_MASK                              0x0F0F0707U
+#define LPDDR4__DENALI_PI_295_WRITE_MASK                             0x0F0F0707U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_2__REG DENALI_PI_295
+#define LPDDR4__PI_MEMDATA_RATIO_2__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2
+
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_MASK               0x00000700U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_3__REG DENALI_PI_295
+#define LPDDR4__PI_MEMDATA_RATIO_3__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3
+
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_MASK                0x000F0000U
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_WIDTH                        4U
+#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_295
+#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_MASK                0x0F000000U
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_WIDTH                        4U
+#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_295
+#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_PI_296_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_MASK                0x0000000FU
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_WIDTH                        4U
+#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_MASK                0x00000F00U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_WIDTH                        4U
+#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_MASK                0x000F0000U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_WIDTH                        4U
+#define LPDDR4__PI_ODT_RD_MAP_CS2__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_RD_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_MASK                0x0F000000U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_WIDTH                        4U
+#define LPDDR4__PI_ODT_WR_MAP_CS2__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_WR_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2
+
+#define LPDDR4__DENALI_PI_297_READ_MASK                              0x7F7F0F0FU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK                             0x7F7F0F0FU
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_MASK                0x0000000FU
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_WIDTH                        4U
+#define LPDDR4__PI_ODT_RD_MAP_CS3__REG DENALI_PI_297
+#define LPDDR4__PI_ODT_RD_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3
+
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_MASK                0x00000F00U
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_WIDTH                        4U
+#define LPDDR4__PI_ODT_WR_MAP_CS3__REG DENALI_PI_297
+#define LPDDR4__PI_ODT_WR_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3
+
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_297
+#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0
+
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_297
+#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1
+
+#define LPDDR4__DENALI_PI_298_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_MASK               0x0000007FU
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_2__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV0_2__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_MASK               0x00007F00U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_3__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV0_3__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1
+
+#define LPDDR4__DENALI_PI_299_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_MASK               0x0000007FU
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_2__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV1_2__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_MASK               0x00007F00U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_3__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV1_3__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV2_0__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV2_0__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV2_1__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV2_1__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1
+
+#define LPDDR4__DENALI_PI_300_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_300_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_MASK               0x0000007FU
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV2_2__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV2_2__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_MASK               0x00007F00U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV2_3__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV2_3__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV3_0__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV3_0__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV3_1__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV3_1__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1
+
+#define LPDDR4__DENALI_PI_301_READ_MASK                              0x03037F7FU
+#define LPDDR4__DENALI_PI_301_WRITE_MASK                             0x03037F7FU
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_MASK               0x0000007FU
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV3_2__REG DENALI_PI_301
+#define LPDDR4__PI_VREF_VAL_DEV3_2__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2
+
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_MASK               0x00007F00U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV3_3__REG DENALI_PI_301
+#define LPDDR4__PI_VREF_VAL_DEV3_3__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3
+
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_301
+#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0
+
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_MASK               0x03000000U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_301
+#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1
+
+#define LPDDR4__DENALI_PI_302_READ_MASK                              0x3F3F0303U
+#define LPDDR4__DENALI_PI_302_WRITE_MASK                             0x3F3F0303U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_2__REG DENALI_PI_302
+#define LPDDR4__PI_SLICE_PER_DEV_2__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2
+
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_SHIFT                       8U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_3__REG DENALI_PI_302
+#define LPDDR4__PI_SLICE_PER_DEV_3__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3
+
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_302
+#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0
+
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_MASK                  0x3F000000U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_302
+#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1
+
+#define LPDDR4__DENALI_PI_303_READ_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_303_WRITE_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_2__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_0_2__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_MASK                  0x00003F00U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_SHIFT                          8U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_3__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_0_3__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_MASK                  0x3F000000U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1
+
+#define LPDDR4__DENALI_PI_304_READ_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_304_WRITE_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_2__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_1_2__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_MASK                  0x00003F00U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_SHIFT                          8U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_3__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_1_3__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_2_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_2_0__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_MASK                  0x3F000000U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_2_1__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_2_1__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1
+
+#define LPDDR4__DENALI_PI_305_READ_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_305_WRITE_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_2_2__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_2_2__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_MASK                  0x00003F00U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_SHIFT                          8U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_2_3__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_2_3__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_3_0__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_3_0__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_MASK                  0x3F000000U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_3_1__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_3_1__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1
+
+#define LPDDR4__DENALI_PI_306_READ_MASK                              0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_306_WRITE_MASK                             0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_3_2__REG DENALI_PI_306
+#define LPDDR4__PI_MR6_VREF_3_2__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2
+
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_MASK                  0x00003F00U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_SHIFT                          8U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_3_3__REG DENALI_PI_306
+#define LPDDR4__PI_MR6_VREF_3_3__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3
+
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_307_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_307_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_308_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_308_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_309_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_309_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_310_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_310_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_310
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_310
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_311_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_311_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_311
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_311__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR13_DATA_2
+
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR15_DATA_2
+
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR16_DATA_2
+
+#define LPDDR4__DENALI_PI_312_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_312_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_312
+#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR17_DATA_2
+
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_312
+#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR20_DATA_2
+
+#define LPDDR4__DENALI_PI_313_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_313_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_313
+#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR32_DATA_2
+
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_313
+#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR40_DATA_2
+
+#define LPDDR4__DENALI_PI_314_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_314_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_SHIFT                           0U
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR13_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_SHIFT                           8U
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR15_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_SHIFT                          16U
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR16_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_SHIFT                          24U
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR17_DATA_3
+
+#define LPDDR4__DENALI_PI_315_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_315_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_SHIFT                           0U
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_315
+#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR20_DATA_3
+
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_SHIFT                           8U
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_315
+#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR32_DATA_3
+
+#define LPDDR4__DENALI_PI_316_READ_MASK                              0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_316_WRITE_MASK                             0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_SHIFT                           0U
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_316
+#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_316__PI_MR40_DATA_3
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_MASK                     0x1F000000U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_SHIFT                            24U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_2
+
+#define LPDDR4__DENALI_PI_317_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_317_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_SHIFT                             0U
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_317
+#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_317__PI_CKE_MUX_3
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_SHIFT                              8U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_SHIFT                             16U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_SHIFT                             24U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_2
+
+#define LPDDR4__DENALI_PI_318_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_318_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_MASK                      0x0000001FU
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_SHIFT                              0U
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_318
+#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_318__PI_CS_MUX_3
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_0
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_1
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_MASK                     0x1F000000U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_SHIFT                            24U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_2__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_2__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_2
+
+#define LPDDR4__DENALI_PI_319_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_319_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_SHIFT                             0U
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_3__REG DENALI_PI_319
+#define LPDDR4__PI_ODT_MUX_3__FLD LPDDR4__DENALI_PI_319__PI_ODT_MUX_3
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_MASK                 0x00001F00U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_SHIFT                         8U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_MASK                 0x001F0000U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2
+
+#define LPDDR4__DENALI_PI_320_READ_MASK                              0x01FFFF1FU
+#define LPDDR4__DENALI_PI_320_WRITE_MASK                             0x01FFFF1FU
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_320
+#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3
+
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_MASK               0x01FFFF00U
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_320
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_321_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_321_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_321
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_322_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_322_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_322
+#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2
+
+#define LPDDR4__DENALI_PI_323_READ_MASK                              0x0F01FFFFU
+#define LPDDR4__DENALI_PI_323_WRITE_MASK                             0x0F01FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_323
+#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3
+
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_323
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_324_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_324_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_SHIFT                   24U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2
+
+#define LPDDR4__DENALI_PI_325_READ_MASK                              0x000F0F0FU
+#define LPDDR4__DENALI_PI_325_WRITE_MASK                             0x000F0F0FU
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2
+
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_SHIFT                    8U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3
+
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_SHIFT                   16U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3
+
+#define LPDDR4__DENALI_PI_326_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_326_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT                0U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_326
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT               16U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_326
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0
+
+#define LPDDR4__DENALI_PI_327_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_327_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT                0U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_327
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT               16U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_327
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1
+
+#define LPDDR4__DENALI_PI_328_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_328_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_328
+#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_329_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_329_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_329
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_330_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_330_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_330
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_331_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_331_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_331
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_332_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_332_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_332
+#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_333_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_333_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_333
+#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_334_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_334_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_334
+#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_334
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_335_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_336_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_336_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_336
+#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_337_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_337_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_337
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_338_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_338_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_338
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_339_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_339_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_339
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_340_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_340_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_340
+#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_341_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_341_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_341
+#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_342_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_342_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_342
+#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_342
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_343_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_344_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_344_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_344
+#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_345_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_345_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_345
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_346_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_346_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_346
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_347_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_347_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_347
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_348_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_348_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_348
+#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_349_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_349_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_349
+#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_350_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_350_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_350
+#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_350
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_351_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_352_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_352_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_352
+#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_353_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_353_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_353
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_354_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_354_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_354
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_355_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_355_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_355
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_356_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_356_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_356
+#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_357_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_357_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_357
+#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_358_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_358_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_358
+#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_358
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_359_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_360_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_360_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_360
+#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_361_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_361_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_361
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_362_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_362_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_362
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_363_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_363_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_363
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_364_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_364_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_364
+#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_365_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_365_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_365
+#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_366_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_366_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_366
+#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_366
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_367_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_368_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_368_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_368
+#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_369_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_369_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_369
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_370_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_370_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_370
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_371_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_371_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_371
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_372_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_372_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_372
+#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_373_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_373_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_373
+#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_374_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_374_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_374
+#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_374
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_375_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_376_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_376_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_2__REG DENALI_PI_376
+#define LPDDR4__PI_MR0_DATA_F0_2__FLD LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_377_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_377_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_377
+#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_378_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_378_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_378
+#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_379_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_379_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_379
+#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_380_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_380_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_2__REG DENALI_PI_380
+#define LPDDR4__PI_MR4_DATA_F0_2__FLD LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_381_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_381_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_2__REG DENALI_PI_381
+#define LPDDR4__PI_MR5_DATA_F0_2__FLD LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_382_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_382_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_2__REG DENALI_PI_382
+#define LPDDR4__PI_MR6_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_382
+#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_383_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_384_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_384_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_2__REG DENALI_PI_384
+#define LPDDR4__PI_MR0_DATA_F1_2__FLD LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_385_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_385_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_385
+#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_386_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_386_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_386
+#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_387_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_387_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_387
+#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_388_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_388_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_2__REG DENALI_PI_388
+#define LPDDR4__PI_MR4_DATA_F1_2__FLD LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_389_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_389_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_2__REG DENALI_PI_389
+#define LPDDR4__PI_MR5_DATA_F1_2__FLD LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_390_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_390_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_2__REG DENALI_PI_390
+#define LPDDR4__PI_MR6_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_390
+#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_391_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_392_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_392_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_2__REG DENALI_PI_392
+#define LPDDR4__PI_MR0_DATA_F2_2__FLD LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_393_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_393_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_393
+#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_394_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_394_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_394
+#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_395_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_395_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_395
+#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_396_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_396_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_2__REG DENALI_PI_396
+#define LPDDR4__PI_MR4_DATA_F2_2__FLD LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_397_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_397_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_2__REG DENALI_PI_397
+#define LPDDR4__PI_MR5_DATA_F2_2__FLD LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_398_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_398_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_2__REG DENALI_PI_398
+#define LPDDR4__PI_MR6_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_398
+#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_399_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_400_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_400_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_3__REG DENALI_PI_400
+#define LPDDR4__PI_MR0_DATA_F0_3__FLD LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_401_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_401_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_401
+#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_402_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_402_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_402
+#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_403_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_403_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_403
+#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_404_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_404_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_3__REG DENALI_PI_404
+#define LPDDR4__PI_MR4_DATA_F0_3__FLD LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_405_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_405_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_3__REG DENALI_PI_405
+#define LPDDR4__PI_MR5_DATA_F0_3__FLD LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_406_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_406_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_3__REG DENALI_PI_406
+#define LPDDR4__PI_MR6_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_406
+#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_407_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_408_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_408_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_3__REG DENALI_PI_408
+#define LPDDR4__PI_MR0_DATA_F1_3__FLD LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_409_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_409_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_409
+#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_410_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_410_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_410
+#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_411_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_411_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_411
+#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_412_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_412_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_3__REG DENALI_PI_412
+#define LPDDR4__PI_MR4_DATA_F1_3__FLD LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_413_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_413_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_3__REG DENALI_PI_413
+#define LPDDR4__PI_MR5_DATA_F1_3__FLD LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_414_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_414_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_3__REG DENALI_PI_414
+#define LPDDR4__PI_MR6_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_414
+#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_415_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_416_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_416_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_3__REG DENALI_PI_416
+#define LPDDR4__PI_MR0_DATA_F2_3__FLD LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_417_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_417_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_417
+#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_418_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_418_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_418
+#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_419_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_419_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_419
+#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_420_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_420_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_3__REG DENALI_PI_420
+#define LPDDR4__PI_MR4_DATA_F2_3__FLD LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_421_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_421_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_3__REG DENALI_PI_421
+#define LPDDR4__PI_MR5_DATA_F2_3__FLD LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_422_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_422_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_3__REG DENALI_PI_422
+#define LPDDR4__PI_MR6_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_422
+#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_423_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h
index f22a20a..e233c5b 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h
index df5ab95..8d5196a 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h
index 924013e..5e781e6 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h
similarity index 82%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h
index d46b77b..9ea46fe 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_RW_MASKS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h
similarity index 94%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h
index 94202c9..4db3125 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h
@@ -2,12 +2,12 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#ifndef LPDDR4_16BIT_IF_H
-#define LPDDR4_16BIT_IF_H
+#ifndef LPDDR4_AM64_IF_H
+#define LPDDR4_AM64_IF_H
 
 #include <linux/types.h>
 
@@ -105,4 +105,4 @@
 	LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT		= 28U
 } lpddr4_intr_phyindepinterrupt;
 
-#endif  /* LPDDR4_16BIT_IF_H */
+#endif  /* LPDDR4_AM64_IF_H */
diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
new file mode 100644
index 0000000..e2a23c3
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM64_OBJ_IF_H
+#define LPDDR4_AM64_OBJ_IF_H
+
+#include "lpddr4_am64_if.h"
+
+#endif  /* LPDDR4_AM64_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
new file mode 100644
index 0000000..53b76f0
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM64_STRUCTS_IF_H
+#define LPDDR4_AM64_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_am64_if.h"
+
+#endif  /* LPDDR4_AM64_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h
index 21e96c9..bd29fad 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_CTL_REGS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h
index d3bf24e..c735858 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h
index d60bb6a..bf919af 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h
index 3df803e..b006526 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h
index dcfd7d9..1cf9529 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
rename to drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h
index 9aa281a..9c240d3 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_PI_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
index 298aa5e..94a1619 100644
--- a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
+++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef CPS_DRV_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h
index 58ba340..7fd3f1a 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h
index 4113608..9363035 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_CTL_REGS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h
index ad45dd9..73c027b 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h
index 5385e1e..c199975 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h
index f6edad4..ff534b0 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h
index 73e5f71..800c2a8 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h
index 4e33d04..f0a4fa0 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h
similarity index 82%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h
index 7112294..f760ed8 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_RW_MASKS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h
similarity index 92%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h
index f14ca24..3d738c5 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h
@@ -2,12 +2,12 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#ifndef LPDDR4_32BIT_IF_H
-#define LPDDR4_32BIT_IF_H
+#ifndef LPDDR4_J721E_IF_H
+#define LPDDR4_J721E_IF_H
 
 #include <linux/types.h>
 
@@ -88,4 +88,4 @@
 	LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
 } lpddr4_intr_phyindepinterrupt;
 
-#endif  /* LPDDR4_32BIT_IF_H */
+#endif  /* LPDDR4_J721E_IF_H */
diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
new file mode 100644
index 0000000..8b38ceb
--- /dev/null
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_J721E_OBJ_IF_H
+#define LPDDR4_J721E_OBJ_IF_H
+
+#include "lpddr4_j721e_if.h"
+
+#endif  /* LPDDR4_J721E_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
new file mode 100644
index 0000000..c877195
--- /dev/null
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_J721E_STRUCTS_IF_H
+#define LPDDR4_J721E_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_j721e_if.h"
+
+#endif  /* LPDDR4_J721E_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h
index d8c7a52..d1a9e74 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h
similarity index 99%
rename from drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
rename to drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h
index 7f1754a..8e428cb 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_PI_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
index 78ad966..11ef242 100644
--- a/drivers/ram/k3-ddrss/lpddr4.c
+++ b/drivers/ram/k3-ddrss/lpddr4.c
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <errno.h>
@@ -13,14 +13,6 @@
 #include "lpddr4.h"
 #include "lpddr4_structs_if.h"
 
-#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
-#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
-#endif
-
-#ifndef LPDDR4_CPS_NS_DELAY_TIME
-#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
-#endif
-
 static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
 static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
 static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
@@ -51,10 +43,7 @@
 static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
 static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
 static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
-#ifdef REG_WRITE_VERIF
 static u32 lpddr4_getphyrwmask(u32 regoffset);
-static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
-#endif
 
 u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
 {
@@ -202,8 +191,6 @@
 	return result;
 }
 
-#ifdef REG_WRITE_VERIF
-
 static u32 lpddr4_getphyrwmask(u32 regoffset)
 {
 	u32 rwmask = 0U;
@@ -231,33 +218,43 @@
 	return rwmask;
 }
 
-static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount)
 {
 	u32 result = (u32)0;
+	u32 aindex;
 	u32 regreadval = 0U;
 	u32 rwmask = 0U;
 
-	result = lpddr4_readreg(pd, cpp, regoffset, &regreadval);
+	result = lpddr4_deferredregverifysf(pd, cpp);
 
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
 	if (result == (u32)0) {
-		switch (cpp) {
-		case LPDDR4_PHY_INDEP_REGS:
-			rwmask = g_lpddr4_pi_rw_mask[regoffset];
-			break;
-		case LPDDR4_PHY_REGS:
-			rwmask = lpddr4_getphyrwmask(regoffset);
-			break;
-		default:
-			rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
-			break;
-		}
+		for (aindex = 0; aindex < regcount; aindex++) {
+			result = lpddr4_readreg(pd, cpp, (u32)regnum[aindex], &regreadval);
 
-		if ((rwmask & regreadval) != (regvalue & rwmask))
-			result = EIO;
+			if (result == (u32)0) {
+				switch (cpp) {
+				case LPDDR4_PHY_INDEP_REGS:
+					rwmask = g_lpddr4_pi_rw_mask[(u32)regnum[aindex]];
+					break;
+				case LPDDR4_PHY_REGS:
+					rwmask = lpddr4_getphyrwmask((u32)regnum[aindex]);
+					break;
+				default:
+					rwmask = g_lpddr4_ddr_controller_rw_mask[(u32)regnum[aindex]];
+					break;
+				}
+
+				if ((rwmask & regreadval) != ((u32)(regvalues[aindex]) & rwmask)) {
+					result = EIO;
+					break;
+				}
+			}
+		}
 	}
 	return result;
 }
-#endif
 
 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
 {
@@ -284,11 +281,6 @@
 				CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
 		}
 	}
-#ifdef REG_WRITE_VERIF
-	if (result == (u32)0)
-		result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
-
-#endif
 
 	return result;
 }
@@ -346,9 +338,6 @@
 		}
 	}
 
-#ifdef ASILC
-#endif
-
 	return result;
 }
 
diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h
index 5b77ea9..0fcd6d7 100644
--- a/drivers/ram/k3-ddrss/lpddr4.h
+++ b/drivers/ram/k3-ddrss/lpddr4.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_H
@@ -11,19 +11,13 @@
 
 #include "lpddr4_ctl_regs.h"
 #include "lpddr4_sanity.h"
-#ifdef CONFIG_K3_AM64_DDRSS
-#include "lpddr4_16bit.h"
-#include "lpddr4_16bit_sanity.h"
-#else
-#include "lpddr4_32bit.h"
-#include "lpddr4_32bit_sanity.h"
-#endif
 
-#ifdef REG_WRITE_VERIF
-#include "lpddr4_ctl_regs_rw_masks.h"
-#endif
-#ifdef __cplusplus
-extern "C" {
+#if defined (CONFIG_K3_AM64_DDRSS) || defined (CONFIG_K3_AM62A_DDRSS)
+#include "lpddr4_am6x.h"
+#include "lpddr4_am6x_sanity.h"
+#else
+#include "lpddr4_j721e.h"
+#include "lpddr4_j721e_sanity.h"
 #endif
 
 #define PRODUCT_ID (0x1046U)
@@ -56,6 +50,14 @@
 #define CDN_TRUE  1U
 #define CDN_FALSE 0U
 
+#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
+#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
+#endif
+
+#ifndef LPDDR4_CPS_NS_DELAY_TIME
+#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
+#endif
+
 void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
 volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
 u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
@@ -66,8 +68,5 @@
 void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
 u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
 u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
-#ifdef __cplusplus
-}
-#endif
 
 #endif  /* LPDDR4_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.h b/drivers/ram/k3-ddrss/lpddr4_16bit.h
deleted file mode 100644
index d663389..0000000
--- a/drivers/ram/k3-ddrss/lpddr4_16bit.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_H
-#define LPDDR4_16BIT_H
-
-#define DSLICE_NUM (2U)
-#define ASLICE_NUM (3U)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DSLICE0_REG_COUNT  (126U)
-#define DSLICE1_REG_COUNT  (126U)
-#define ASLICE0_REG_COUNT  (42U)
-#define ASLICE1_REG_COUNT  (42U)
-#define ASLICE2_REG_COUNT  (42U)
-#define PHY_CORE_REG_COUNT (126U)
-
-#define GRP_SHIFT 1
-#define INT_SHIFT 2
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPDDR4_16BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_32bit.h
deleted file mode 100644
index 1f7fe65..0000000
--- a/drivers/ram/k3-ddrss/lpddr4_32bit.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_32BIT_H
-#define LPDDR4_32BIT_H
-
-#define DSLICE_NUM (4U)
-#define ASLICE_NUM (1U)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DSLICE0_REG_COUNT  (140U)
-#define DSLICE1_REG_COUNT  (140U)
-#define DSLICE2_REG_COUNT  (140U)
-#define DSLICE3_REG_COUNT  (140U)
-#define ASLICE0_REG_COUNT  (52U)
-#define PHY_CORE_REG_COUNT (140U)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* LPDDR4_32BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
similarity index 69%
copy from drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
copy to drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
index 09b0e3c..2b871cc 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
+++ b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
@@ -2,12 +2,12 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/types.h>
-#include "lpddr4_ctl_regs_rw_masks.h"
+#include <lpddr4_am62a_ctl_regs_rw_masks.h>
 
 u32 g_lpddr4_ddr_controller_rw_mask[] = {
 	0x00000F01U,
@@ -48,6 +48,8 @@
 	0x0000FFFFU,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
+	0x00000000U,
 	0x0F3F7F7FU,
 	0xFFFFFFFFU,
 	0x0F3F7F7FU,
@@ -98,29 +100,27 @@
 	0x0FFFFF01U,
 	0x001F1F01U,
 	0xFFFFFFFFU,
-	0x0000FFFFU,
-	0x00000000U,
-	0x1FFFFFFFU,
-	0x1F0F1F1FU,
-	0x1F0F1F1FU,
-	0x1F0F1F1FU,
-	0x1F011F01U,
+	0xFFFFFFFFU,
+	0x1F1F1FFFU,
+	0x1F1F1F0FU,
+	0x1F1F1F0FU,
+	0x1F011F0FU,
+	0x00011F01U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x07FFFFFFU,
+	0x1F1F1F1FU,
+	0x1F07FF1FU,
+	0x1F1F1F1FU,
+	0x1F1F07FFU,
+	0x1F1F1F1FU,
+	0x01011F1FU,
+	0x7F000701U,
 	0x00FFFF01U,
 	0xFFFFFFFFU,
-	0xFFFFFFFFU,
-	0xFFFFFFFFU,
-	0xFFFFFFFFU,
-	0x1F1F07FFU,
-	0xFF1F1F1FU,
-	0x1F1F1F07U,
-	0x07FF1F1FU,
-	0x1F1F1F1FU,
-	0x1F1F1F1FU,
-	0x07010101U,
-	0x00017F00U,
-	0xFFFFFFFFU,
-	0x0700FFFFU,
-	0xFFFFFF07U,
+	0xFF070700U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -128,7 +128,7 @@
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
-	0x0000FFFFU,
+	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -162,10 +162,12 @@
 	0x01FFFFFFU,
 	0x0000FF00U,
 	0x0001FFFFU,
-	0x0F01FFFFU,
+	0x0F03FFFFU,
 	0x00000001U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
 	0xFFFF0100U,
 	0xFFFFFFFFU,
 	0x0F0F0003U,
@@ -201,7 +203,8 @@
 	0x07FFFFFFU,
 	0x01FFFF00U,
 	0x00000000U,
-	0x00030100U,
+	0x00000000U,
+	0x03010000U,
 	0x03FF03FFU,
 	0x1F1F03FFU,
 	0x000FFFFFU,
@@ -293,11 +296,14 @@
 	0x3F000003U,
 	0x00000101U,
 	0xFFFFFFFFU,
-	0x00000001U,
+	0x00000007U,
+	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0x00000007U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
 	0x000FFF00U,
 	0x1F000000U,
 	0x1F1F1F1FU,
@@ -338,12 +344,14 @@
 	0x03010101U,
 	0x0301011FU,
 	0x07010F03U,
-	0x03030307U,
-	0x03011F03U,
+	0x0F0F0F07U,
+	0x0F0F0F0FU,
+	0x03011F0FU,
 	0x01010000U,
 	0x01030303U,
 	0x00000101U,
-	0x00010000U,
+	0x01000000U,
+	0x00000000U,
 	0x00000000U,
 	0xFFFFFFFFU,
 	0x00000000U,
@@ -380,6 +388,10 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
 	0xFF000000U,
 	0x0FFF0F0FU,
 	0x0F0FFF0FU,
@@ -403,7 +415,7 @@
 	0x007FFFFFU,
 	0xFFFFFFFFU,
 	0xFFFF070FU,
-	0x00FFFFFFU,
+	0xFF7FFFFFU,
 	0x001FFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -412,7 +424,7 @@
 	0x007FFFFFU,
 	0xFFFFFFFFU,
 	0xFFFF070FU,
-	0x00FFFFFFU,
+	0xFF7FFFFFU,
 	0x001FFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -421,18 +433,18 @@
 	0x007FFFFFU,
 	0xFFFFFFFFU,
 	0xFFFF070FU,
-	0xFFFFFFFFU,
-	0x000300FFU,
-	0x0F0FFFFFU,
-	0x0701FF07U,
-	0x07070707U,
-	0x0F0F0F07U,
+	0x007FFFFFU,
+	0x00FFFFFFU,
+	0x0FFFFF03U,
+	0x01FF070FU,
+	0x07070701U,
+	0x0F070707U,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
-	0xFFFFFF0FU,
-	0x007F7F7FU
+	0xFF0F0F0FU,
+	0x0000FFFFU
 };
 
 u32 g_lpddr4_pi_rw_mask[] = {
@@ -449,28 +461,31 @@
 	0x00000000U,
 	0x0000011FU,
 	0xFFFFFFFFU,
-	0x01030101U,
-	0x0F011F03U,
+	0x010F0101U,
+	0x0F011F0FU,
 	0x0101070FU,
 	0x000FFFFFU,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x00000007U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
+	0x00000000U,
 	0x01000000U,
-	0x00010101U,
-	0x3F3F0103U,
-	0x0101FFFFU,
-	0x01030103U,
-	0x0000FF00U,
+	0x01010101U,
+	0x3F030F00U,
+	0x01FFFF3FU,
+	0x0F010F01U,
+	0x00FF0001U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
-	0x030F0F1FU,
-	0x00000003U,
+	0x0F0F0F1FU,
+	0x0000000FU,
 	0x03FFFFFFU,
 	0x00000F07U,
-	0x00000103U,
+	0x0000030FU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -481,18 +496,18 @@
 	0xFFFFFFFFU,
 	0x0101010FU,
 	0x01010101U,
-	0x00030301U,
+	0x000F0F01U,
 	0x000003FFU,
 	0xFFFFFFFFU,
-	0x0000FF03U,
+	0x0000FF0FU,
 	0xFFFFFFFFU,
 	0x00FFFF00U,
 	0x0F0FFFFFU,
 	0x01011F1FU,
-	0x03000000U,
-	0x030F0101U,
+	0x0F000000U,
+	0x030F0103U,
 	0x01010101U,
-	0x0000FF03U,
+	0x0000FF0FU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFF0001U,
@@ -500,25 +515,26 @@
 	0xFF0F0F01U,
 	0x017F1FFFU,
 	0xFF01FFFFU,
-	0x01010101U,
-	0x030701FFU,
-	0x1F1F0301U,
-	0x01030001U,
+	0x01010103U,
+	0x0F0701FFU,
+	0x1F1F0F01U,
+	0x030F0001U,
 	0x000000FFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0x0101FFFFU,
 	0x00030001U,
 	0xFFFFFFFFU,
-	0x00010101U,
+	0x00010107U,
 	0x010003FFU,
 	0x01010101U,
-	0x1F070303U,
+	0x07030F01U,
+	0x0F0F0F1FU,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
 	0x0F0F0F0FU,
-	0x0F0F0F0FU,
+	0x0000000FU,
 	0x00000000U,
 	0x00000000U,
 	0x3FFFFFFFU,
@@ -527,40 +543,48 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
 	0x011F3F00U,
 	0x1F1F1F1FU,
 	0x1F1F1F1FU,
-	0x0101011FU,
-	0x00FFFF01U,
-	0x00000107U,
-	0x000101FFU,
+	0x0303011FU,
+	0x00010303U,
+	0x0700FFFFU,
+	0xFF000001U,
+	0x00000101U,
 	0xFFFFFFFFU,
-	0x0000FF01U,
+	0x0000FF07U,
+	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0x0FFF0000U,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x00000003U,
+	0x0000000FU,
 	0xFFFFFFFFU,
-	0x03030703U,
+	0x0303070FU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
-	0x0000003FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000007FU,
 	0x3FFFFFFFU,
 	0x3FFFFFFFU,
 	0x3FFFFFFFU,
@@ -580,7 +604,7 @@
 	0x00000100U,
 	0x0001FFFFU,
 	0x01000000U,
-	0x01000003U,
+	0x0100000FU,
 	0x00010F07U,
 	0x0F00010FU,
 	0x010F0001U,
@@ -598,9 +622,9 @@
 	0x00FF0101U,
 	0x000001FFU,
 	0x0000001FU,
-	0x01031F01U,
+	0x0F011F01U,
 	0x01010101U,
-	0x00FFFF07U,
+	0xFFFF0701U,
 	0xFFFFFFFFU,
 	0x00FFFFFFU,
 	0x000000FFU,
@@ -719,19 +743,86 @@
 	0x0FFF0FFFU,
 	0x030F0F0FU,
 	0x07070303U,
-	0x03030303U,
+	0x0F0F0707U,
+	0x0F0F0F0FU,
+	0x7F7F0F0FU,
 	0x7F7F7F7FU,
+	0x7F7F7F7FU,
+	0x7F7F7F7FU,
+	0x03037F7FU,
 	0x00000303U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
 	0xFFFF0000U,
 	0x00FFFFFFU,
 	0xFF01FFFFU,
 	0xFFFFFFFFU,
 	0x01FFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x01FFFFFFU,
 	0x1F1F1FFFU,
 	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
 	0x01FFFF1FU,
-	0x0301FFFFU,
-	0x00030303U,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0F01FFFFU,
+	0x0F0F0F0FU,
+	0x000F0F0FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
 	0xFFFFFFFFU,
 	0x0001FFFFU,
 	0x0001FFFFU,
@@ -789,10 +880,11 @@
 	0x010303FFU,
 	0x3F3F3F3FU,
 	0x3F3F3F3FU,
-	0x1F030F3FU,
-	0x030F0F1FU,
-	0x01FF031FU,
-	0x00000101U,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0x00000001U,
 	0xFFFFFFFFU,
 	0x00000000U,
 	0x7F0101FFU,
@@ -802,7 +894,7 @@
 	0x01FF0701U,
 	0x00000003U,
 	0x00000000U,
-	0x00000003U,
+	0x00000301U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -845,6 +937,7 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x7FFFFFFFU,
 	0x0000003FU,
 	0x00000000U,
@@ -856,8 +949,11 @@
 	0x000001FFU,
 	0x0003FFFFU,
 	0x01FF01FFU,
-	0x071F07FFU,
-	0x01010101U,
+	0xFF1F07FFU,
+	0xFF3F03FFU,
+	0x010101FFU,
+	0x01010703U,
+	0x00000101U,
 	0x07FFFF07U,
 	0x7F03FFFFU,
 	0xFF01037FU,
@@ -872,12 +968,13 @@
 	0x03FF03FFU,
 	0x03FF03FFU,
 	0x1F0703FFU,
+	0x00000007U,
 	0xFFFFFFFFU,
 	0xFFFFFF0FU,
 	0x0FFFFFFFU,
-	0x0303FFFFU,
-	0x1F1F0103U,
-	0x000F1F1FU,
+	0x03FFFF01U,
+	0x1F010303U,
+	0x0F1F1F1FU,
 	0xFF3F07FFU,
 	0x0FFF0FFFU,
 	0x001F0F3FU,
@@ -885,8 +982,10 @@
 	0x01FF0FFFU,
 	0x00000F01U,
 	0x000003FFU,
-	0x7F7F0703U,
-	0x0000001FU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F7F7FU,
 	0xFFFFFFFFU,
 	0x0000000FU,
 	0x07FF07FFU,
@@ -909,7 +1008,10 @@
 	0x000F03FFU,
 	0x010F07FFU,
 	0x000003FFU,
-	0x003FFFFFU
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
 };
 
 u32 g_lpddr4_data_slice_1_rw_mask[] = {
@@ -918,10 +1020,11 @@
 	0x010303FFU,
 	0x3F3F3F3FU,
 	0x3F3F3F3FU,
-	0x1F030F3FU,
-	0x030F0F1FU,
-	0x01FF031FU,
-	0x00000101U,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0x00000001U,
 	0xFFFFFFFFU,
 	0x00000000U,
 	0x7F0101FFU,
@@ -931,7 +1034,7 @@
 	0x01FF0701U,
 	0x00000003U,
 	0x00000000U,
-	0x00000003U,
+	0x00000301U,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
 	0xFFFFFFFFU,
@@ -974,6 +1077,7 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x7FFFFFFFU,
 	0x0000003FU,
 	0x00000000U,
@@ -985,8 +1089,11 @@
 	0x000001FFU,
 	0x0003FFFFU,
 	0x01FF01FFU,
-	0x071F07FFU,
-	0x01010101U,
+	0xFF1F07FFU,
+	0xFF3F03FFU,
+	0x010101FFU,
+	0x01010703U,
+	0x00000101U,
 	0x07FFFF07U,
 	0x7F03FFFFU,
 	0xFF01037FU,
@@ -1001,12 +1108,13 @@
 	0x03FF03FFU,
 	0x03FF03FFU,
 	0x1F0703FFU,
+	0x00000007U,
 	0xFFFFFFFFU,
 	0xFFFFFF0FU,
 	0x0FFFFFFFU,
-	0x0303FFFFU,
-	0x1F1F0103U,
-	0x000F1F1FU,
+	0x03FFFF01U,
+	0x1F010303U,
+	0x0F1F1F1FU,
 	0xFF3F07FFU,
 	0x0FFF0FFFU,
 	0x001F0F3FU,
@@ -1014,8 +1122,10 @@
 	0x01FF0FFFU,
 	0x00000F01U,
 	0x000003FFU,
-	0x7F7F0703U,
-	0x0000001FU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F7F7FU,
 	0xFFFFFFFFU,
 	0x0000000FU,
 	0x07FF07FFU,
@@ -1038,7 +1148,290 @@
 	0x000F03FFU,
 	0x010F07FFU,
 	0x000003FFU,
-	0x003FFFFFU
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_2_rw_mask[] = {
+	0x07FF7F07U,
+	0x0703FF0FU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x7F0101FFU,
+	0x010101FFU,
+	0x03FF003FU,
+	0x01FF000FU,
+	0x01FF0701U,
+	0x00000003U,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0x3F030001U,
+	0x0F3FFF0FU,
+	0x1F030F3FU,
+	0x03FFFFFFU,
+	0x00073FFFU,
+	0x0F0F07FFU,
+	0x000FFFFFU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0xFF1F07FFU,
+	0xFF3F03FFU,
+	0x010101FFU,
+	0x01010703U,
+	0x00000101U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x007F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F0703FFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F010303U,
+	0x0F1F1F1FU,
+	0xFF3F07FFU,
+	0x0FFF0FFFU,
+	0x001F0F3FU,
+	0x03FF03FFU,
+	0x01FF0FFFU,
+	0x00000F01U,
+	0x000003FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F7F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_3_rw_mask[] = {
+	0x07FF7F07U,
+	0x0703FF0FU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x7F0101FFU,
+	0x010101FFU,
+	0x03FF003FU,
+	0x01FF000FU,
+	0x01FF0701U,
+	0x00000003U,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0x3F030001U,
+	0x0F3FFF0FU,
+	0x1F030F3FU,
+	0x03FFFFFFU,
+	0x00073FFFU,
+	0x0F0F07FFU,
+	0x000FFFFFU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0xFF1F07FFU,
+	0xFF3F03FFU,
+	0x010101FFU,
+	0x01010703U,
+	0x00000101U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x007F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F0703FFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F010303U,
+	0x0F1F1F1FU,
+	0xFF3F07FFU,
+	0x0FFF0FFFU,
+	0x001F0F3FU,
+	0x03FF03FFU,
+	0x01FF0FFFU,
+	0x00000F01U,
+	0x000003FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F7F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
 };
 
 u32 g_lpddr4_address_slice_0_rw_mask[] = {
@@ -1062,6 +1455,7 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x000FFFFFU,
 	0x000FFFFFU,
 	0x000FFFFFU,
@@ -1073,18 +1467,23 @@
 	0x3FFFFFFFU,
 	0x3F3F03FFU,
 	0x3F0F3F3FU,
-	0x0000003FU,
-	0x0707FFFFU,
+	0xFFFFFF03U,
+	0x01FFFFFFU,
+	0x3F03FFFFU,
+	0x0101FFFFU,
+	0x00003F01U,
+	0x07FF07FFU,
+	0x07FF1F07U,
 	0x1F07FF1FU,
 	0x001F07FFU,
 	0x001F07FFU,
 	0x001F07FFU,
-	0x001F07FFU,
 	0x000F07FFU,
 	0xFF3F07FFU,
 	0x0103FFFFU,
 	0x0000000FU,
-	0x0000010FU
+	0x03FF010FU,
+	0x0000FF01U
 };
 
 u32 g_lpddr4_address_slice_1_rw_mask[] = {
@@ -1108,6 +1507,7 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x000FFFFFU,
 	0x000FFFFFU,
 	0x000FFFFFU,
@@ -1119,18 +1519,23 @@
 	0x3FFFFFFFU,
 	0x3F3F03FFU,
 	0x3F0F3F3FU,
-	0x0000003FU,
-	0x0707FFFFU,
+	0xFFFFFF03U,
+	0x01FFFFFFU,
+	0x3F03FFFFU,
+	0x0101FFFFU,
+	0x00003F01U,
+	0x07FF07FFU,
+	0x07FF1F07U,
 	0x1F07FF1FU,
 	0x001F07FFU,
 	0x001F07FFU,
 	0x001F07FFU,
-	0x001F07FFU,
 	0x000F07FFU,
 	0xFF3F07FFU,
 	0x0103FFFFU,
 	0x0000000FU,
-	0x0000010FU
+	0x03FF010FU,
+	0x0000FF01U
 };
 
 u32 g_lpddr4_address_slice_2_rw_mask[] = {
@@ -1154,6 +1559,7 @@
 	0x00000000U,
 	0x00000000U,
 	0x00000000U,
+	0x00000000U,
 	0x000FFFFFU,
 	0x000FFFFFU,
 	0x000FFFFFU,
@@ -1165,18 +1571,23 @@
 	0x3FFFFFFFU,
 	0x3F3F03FFU,
 	0x3F0F3F3FU,
-	0x0000003FU,
-	0x0707FFFFU,
+	0xFFFFFF03U,
+	0x01FFFFFFU,
+	0x3F03FFFFU,
+	0x0101FFFFU,
+	0x00003F01U,
+	0x07FF07FFU,
+	0x07FF1F07U,
 	0x1F07FF1FU,
 	0x001F07FFU,
 	0x001F07FFU,
 	0x001F07FFU,
-	0x001F07FFU,
 	0x000F07FFU,
 	0xFF3F07FFU,
 	0x0103FFFFU,
 	0x0000000FU,
-	0x0000010FU
+	0x03FF010FU,
+	0x0000FF01U
 };
 
 u32 g_lpddr4_phy_core_rw_mask[] = {
@@ -1194,23 +1605,26 @@
 	0x00000000U,
 	0x00000000U,
 	0x0101FF01U,
-	0x0007FF03U,
-	0x070F07FFU,
-	0x01010300U,
-	0x0F010001U,
+	0x0007FF0FU,
+	0xFF0F07FFU,
+	0x01030007U,
+	0xFFFF0101U,
+	0xFF3F0103U,
+	0x010101FFU,
+	0x0F0F0100U,
+	0x0F010F0FU,
 	0x010F0F0FU,
-	0x0F0F0F0FU,
-	0x00010101U,
-	0x010FFFFFU,
-	0x00000001U,
+	0xFFFF0101U,
+	0x0001010FU,
 	0x00000000U,
 	0x0000FFFFU,
 	0x00000001U,
 	0x0F0F0F0FU,
-	0x03030303U,
-	0x03030303U,
-	0x03030303U,
-	0x03030303U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x00FF01FFU,
 	0xFFFF1FFFU,
 	0x0000FF01U,
 	0x00000000U,
@@ -1219,8 +1633,8 @@
 	0x00000000U,
 	0x00000000U,
 	0x0FFF0FFFU,
-	0xFF0F0101U,
-	0x0003FF01U,
+	0x0F010101U,
+	0x03FF01FFU,
 	0x0101FFFFU,
 	0x0003FFFFU,
 	0x0001FFFFU,
@@ -1260,19 +1674,21 @@
 	0x01010000U,
 	0x00000001U,
 	0xFFFFFFFFU,
-	0x03071FFFU,
-	0x00030303U,
+	0x071F01FFU,
+	0x03030303U,
 	0xFFFFFFFFU,
 	0x03FFFFFFU,
 	0x00FF073FU,
 	0x0707FFFFU,
 	0x00000000U,
 	0x00000000U,
-	0x00000003U,
-	0x0F1F0101U,
 	0x00000000U,
+	0x00000000U,
+	0x00000003U,
+	0x1F010101U,
+	0x0000000FU,
 	0x0003FFFFU,
-	0x0007FFFFU,
+	0x0703FFFFU,
 	0x00000001U,
 	0x00011FFFU,
 	0x0F0F0FFFU,
@@ -1287,6 +1703,7 @@
 	0x000007FFU,
 	0x000007FFU,
 	0x000007FFU,
+	0x00000007U,
 	0x3FFFFFFFU,
 	0x0003FFFFU,
 	0x7FFFFFFFU,
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c
similarity index 98%
rename from drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
rename to drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c
index 09b0e3c..249b56d 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
+++ b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c
@@ -2,12 +2,12 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/types.h>
-#include "lpddr4_ctl_regs_rw_masks.h"
+#include <lpddr4_am64_ctl_regs_rw_masks.h>
 
 u32 g_lpddr4_ddr_controller_rw_mask[] = {
 	0x00000F01U,
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.c b/drivers/ram/k3-ddrss/lpddr4_am6x.c
similarity index 97%
rename from drivers/ram/k3-ddrss/lpddr4_16bit.c
rename to drivers/ram/k3-ddrss/lpddr4_am6x.c
index b749b74..8ccc1f1 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit.c
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x.c
@@ -2,19 +2,18 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <errno.h>
-
 #include "cps_drv_lpddr4.h"
 #include "lpddr4_ctl_regs.h"
 #include "lpddr4_if.h"
 #include "lpddr4.h"
 #include "lpddr4_structs_if.h"
 
-static u32 ctlintmap[51][3] = {
+static u16 ctlintmap[51][3] = {
 	{ 0,  0,  7  },
 	{ 1,  0,  8  },
 	{ 2,  0,  9  },
@@ -86,6 +85,7 @@
 	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
 	regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
 	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+
 	return result;
 }
 
@@ -345,15 +345,18 @@
 		result = (u32)EIO;
 	} else {
 		*mrrstatus = (u8)0;
+#ifdef CONFIG_K3_AM64_DDRSS
 		lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
+#else
+		lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
+		*mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
+#endif
 		*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
 		result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
 	}
 	return result;
 }
 
-#ifdef REG_WRITE_VERIF
-
 u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
 {
 	u32 rwmask = 0U;
@@ -370,7 +373,6 @@
 	}
 	return rwmask;
 }
-#endif
 
 u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
 {
diff --git a/drivers/ram/k3-ddrss/lpddr4_am6x.h b/drivers/ram/k3-ddrss/lpddr4_am6x.h
new file mode 100644
index 0000000..bc707d9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM6X_H
+#define LPDDR4_AM6X_H
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#include "lpddr4_am64_ctl_regs_rw_masks.h"
+#elif CONFIG_K3_AM62A_DDRSS
+#include "lpddr4_am62a_ctl_regs_rw_masks.h"
+#endif
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#define DSLICE_NUM (2U)
+#define ASLICE_NUM (2U)
+#define DSLICE0_REG_COUNT  (126U)
+#define DSLICE1_REG_COUNT  (126U)
+#define ASLICE0_REG_COUNT  (42U)
+#define ASLICE1_REG_COUNT  (42U)
+#define ASLICE2_REG_COUNT  (42U)
+#define PHY_CORE_REG_COUNT (126U)
+
+#elif CONFIG_K3_AM62A_DDRSS
+#define DSLICE_NUM (4U)
+#define ASLICE_NUM (3U)
+#define DSLICE0_REG_COUNT  (136U)
+#define DSLICE1_REG_COUNT  (136U)
+#define DSLICE2_REG_COUNT  (136U)
+#define DSLICE3_REG_COUNT  (136U)
+#define ASLICE0_REG_COUNT  (48U)
+#define ASLICE1_REG_COUNT  (48U)
+#define ASLICE2_REG_COUNT  (48U)
+#define PHY_CORE_REG_COUNT (132U)
+
+#endif
+
+#define GRP_SHIFT 1
+#define INT_SHIFT 2
+
+#endif /* LPDDR4_AM6X_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h
similarity index 96%
rename from drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
rename to drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h
index fde05ce..18762cb 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h
@@ -2,19 +2,19 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#ifndef LPDDR4_16BIT_SANITY_H
-#define LPDDR4_16BIT_SANITY_H
+#ifndef LPDDR4_AM6X_SANITY_H
+#define LPDDR4_AM6X_SANITY_H
 
 #include <errno.h>
 #include <linux/types.h>
 #include <lpddr4_if.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
+#include <lpddr4_if.h>
+#include <lpddr4_if.h>
+#include <lpddr4_if.h>
 
 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
@@ -250,8 +250,4 @@
 	return ret;
 }
 
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* LPDDR4_16BIT_SANITY_H */
+#endif  /* LPDDR4_AM6X_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h
index 7562989..1d8bcf7 100644
--- a/drivers/ram/k3-ddrss/lpddr4_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_if.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_IF_H
@@ -11,9 +11,11 @@
 
 #include <linux/types.h>
 #ifdef CONFIG_K3_AM64_DDRSS
-#include <lpddr4_16bit_if.h>
+#include <lpddr4_am64_if.h>
+#elif CONFIG_K3_AM62A_DDRSS
+#include <lpddr4_am62a_if.h>
 #else
-#include <lpddr4_32bit_if.h>
+#include <lpddr4_j721e_if.h>
 #endif
 
 typedef struct lpddr4_config_s lpddr4_config;
@@ -141,4 +143,6 @@
 
 u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
 
+u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
+
 #endif  /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_j721e.c
similarity index 97%
rename from drivers/ram/k3-ddrss/lpddr4_32bit.c
rename to drivers/ram/k3-ddrss/lpddr4_j721e.c
index ab2e448..5db7e5c 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit.c
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e.c
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <errno.h>
@@ -273,8 +273,6 @@
 	return result;
 }
 
-#ifdef REG_WRITE_VERIF
-
 u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
 {
 	u32 rwmask = 0U;
@@ -299,4 +297,3 @@
 	}
 	return rwmask;
 }
-#endif
diff --git a/drivers/ram/k3-ddrss/lpddr4_j721e.h b/drivers/ram/k3-ddrss/lpddr4_j721e.h
new file mode 100644
index 0000000..f115af7
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_J721E_H
+#define LPDDR4_J721E_H
+
+#include "lpddr4_j721e_ctl_regs_rw_masks.h"
+
+#define DSLICE_NUM (4U)
+#define ASLICE_NUM (1U)
+
+#define DSLICE0_REG_COUNT  (140U)
+#define DSLICE1_REG_COUNT  (140U)
+#define DSLICE2_REG_COUNT  (140U)
+#define DSLICE3_REG_COUNT  (140U)
+#define ASLICE0_REG_COUNT  (52U)
+#define PHY_CORE_REG_COUNT (140U)
+
+#endif  /* LPDDR4_J721E_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c
similarity index 99%
rename from drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
rename to drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c
index 70f0ef5..2439474 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c
@@ -2,12 +2,12 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/types.h>
-#include "lpddr4_ctl_regs_rw_masks.h"
+#include <lpddr4_j721e_ctl_regs_rw_masks.h>
 
 u32 g_lpddr4_ddr_controller_rw_mask[] = {
 	0x00000F01U,
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h
similarity index 96%
rename from drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
rename to drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h
index 334eecc..174002f 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h
@@ -2,19 +2,16 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#ifndef LPDDR4_32BIT_SANITY_H
-#define LPDDR4_32BIT_SANITY_H
+#ifndef LPDDR4_J721E_SANITY_H
+#define LPDDR4_J721E_SANITY_H
 
 #include <errno.h>
 #include <linux/types.h>
 #include <lpddr4_if.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
 
 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
@@ -216,8 +213,4 @@
 	return ret;
 }
 
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* LPDDR4_32BIT_SANITY_H */
+#endif  /* LPDDR4_J721E_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
index 370242f..63b259c 100644
--- a/drivers/ram/k3-ddrss/lpddr4_obj_if.c
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "lpddr4_obj_if.h"
@@ -45,6 +45,7 @@
 		.getrefreshrate			= lpddr4_getrefreshrate,
 		.setrefreshrate			= lpddr4_setrefreshrate,
 		.refreshperchipselect		= lpddr4_refreshperchipselect,
+		.deferredregverify		= lpddr4_deferredregverify,
 	};
 
 	return &driver;
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
index d538e61..b1bbb5c 100644
--- a/drivers/ram/k3-ddrss/lpddr4_obj_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef lpddr4_obj_if_h
@@ -79,6 +79,8 @@
 	u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
 
 	u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
+
+	u32 (*deferredregverify)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
 } lpddr4_obj;
 
 extern lpddr4_obj *lpddr4_getinstance(void);
diff --git a/drivers/ram/k3-ddrss/lpddr4_private.h b/drivers/ram/k3-ddrss/lpddr4_private.h
deleted file mode 100644
index 3d5017e..0000000
--- a/drivers/ram/k3-ddrss/lpddr4_private.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#ifndef LPDDR4_PRIV_H
-#define LPDDR4_PRIV_H
-
-#define PRODUCT_ID (0x1046U)
-#define VERSION_0  (0x54d5da40U)
-#define VERSION_1  (0xc1865a1U)
-
-#define LPDDR4_BIT_MASK	(0x1U)
-#define BYTE_MASK	(0xffU)
-#define NIBBLE_MASK	(0xfU)
-
-#define WORD_SHIFT (32U)
-#define WORD_MASK (0xffffffffU)
-#define SLICE_WIDTH (0x100)
-/* Number of Data slices */
-#define DSLICE_NUM (4U)
-/*Number of Address Slices */
-#define ASLICE_NUM (1U)
-
-/* Number of accessible registers in each slice */
-#define DSLICE0_REG_COUNT  (140U)
-#define DSLICE1_REG_COUNT  (140U)
-#define DSLICE2_REG_COUNT  (140U)
-#define DSLICE3_REG_COUNT  (140U)
-#define ASLICE0_REG_COUNT  (52U)
-#define PHY_CORE_REG_COUNT (140U)
-
-#define CTL_OFFSET 0
-#define PI_OFFSET (((uint32_t)1) <<  11)
-#define PHY_OFFSET (((uint32_t)1) << 12)
-
-/* BIT[17] on INT_MASK_1 register. */
-#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
-
-/* Init Error information bits */
-#define PLL_READY (0x3U)
-#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
-#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
-#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
-#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U)
-#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \
-		     ((uint32_t)LPDDR4_BIT_MASK << 4U))
-#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
-#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \
-			       ((uint32_t)LPDDR4_BIT_MASK << 6U))
-#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \
-			       (((uint32_t)BYTE_MASK) << 16U))
-#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \
-		       (((uint32_t)BYTE_MASK) << 18U))
-
-#endif  /* LPDDR4_PRIV_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h
index 750e00d..d5e61ff 100644
--- a/drivers/ram/k3-ddrss/lpddr4_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_SANITY_H
@@ -12,9 +12,6 @@
 #include <errno.h>
 #include <linux/types.h>
 #include "lpddr4_if.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
 
 static inline u32 lpddr4_configsf(const lpddr4_config *obj);
 static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
@@ -37,7 +34,7 @@
 static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
 static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
 static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
-static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val);
 static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
 
 #define lpddr4_probesf lpddr4_sanityfunction1
@@ -70,6 +67,7 @@
 #define lpddr4_getrefreshratesf lpddr4_sanityfunction28
 #define lpddr4_setrefreshratesf lpddr4_sanityfunction29
 #define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
+#define lpddr4_deferredregverifysf lpddr4_sanityfunction5
 
 static inline u32 lpddr4_configsf(const lpddr4_config *obj)
 {
@@ -390,15 +388,15 @@
 	return ret;
 }
 
-static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val)
 {
 	u32 ret = 0;
 
 	if (fspnum == NULL) {
 		ret = EINVAL;
-	} else if (tref == NULL) {
+	} else if (tref_val == NULL) {
 		ret = EINVAL;
-	} else if (tras_max == NULL) {
+	} else if (tras_max_val == NULL) {
 		ret = EINVAL;
 	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
 		ret = EINVAL;
@@ -438,8 +436,4 @@
 	return ret;
 }
 
-#ifdef __cplusplus
-}
-#endif
-
 #endif  /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
index f2f1210..b09e708 100644
--- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -2,8 +2,8 @@
 /*
  * Cadence DDR Driver
  *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef LPDDR4_STRUCTS_IF_H